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STE2004S 数据表(PDF) 4 Page - STMicroelectronics |
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STE2004S 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 79 page  Block diagram STE2004S 4/79 1 Block diagram Figure 1. STE2004S block diagram COLUMN DRIVERS ROW DRIVERS DATA LATCHES 65 x 102 RAM DISPLAY CONTROL LOGIC SCROLL LOGIC DATA REGISTER INSTRUCTION REGISTER CO to C101 R0 to R64 VSENSE SLAVE RES VDD1,2 CLOCK TIMING GENERATOR BIAS VOLTAGE GENERATOR HIGH VOLTAGE GENERATOR RESET TEST SHIFT REGISTER VLCD VSS EXT ICON_MODE VSSAUX SAO SDIN/SDA_IN SDA_OUT SCLK/SCL DB0 to DB7 9 Bit SERIAL D/C CS SA1 SDOUT E/WR R/W- RD I2C BUS 3 & 4 Line SPI Parallel 8080 Parallel 68K SEL 3 SEL 1 SEL 2 TEST_VREF TEST_MODE LR0047 OSC OSC_IN OSC_OUT FR_IN FR_OUT MASTER SLAVE SYNC VLCDSENSE |
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