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ST10F273E 数据表(PDF) 145 Page - STMicroelectronics |
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ST10F273E 数据表(HTML) 145 Page - STMicroelectronics |
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145 / 179 page  ST10F273E Electrical characteristics 145/179 24.8.2 Definition of internal timing The internal operation of the ST10F273E is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (for example pipeline) or external (for example bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F273E. The example for PLL operation shown in Figure 43 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 43. Generation mechanisms for the CPU clock TCLTCL TCLTCL fCPU fXTAL fCPU fXTAL Phase locked loop operation Direct clock drive TCL TCL fCPU fXTAL Prescaler operation |
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