M58BW016DB datasheet(21/69 Pages) STMICROELECTRONICS

21 / 69 page

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

21/69

3.2

Synchronous Bus operations

For Synchronous Bus Operations refer to Table 6 together with the following text.

3.2.1

Synchronous Burst Read

Synchronous Burst Read operations are used to read from the memory at specific times

synchronized to an external reference clock.

In the M58BW016FT and M58BW016FB only, once the memory is configured in Burst

mode, it is mandatory to have an active clock signal since the switching of the output buffer

data bus is synchronized to the active edge of the clock. In the absence of clock, no data is

output.

Caution:

The M58BW016DT and M58BW016DB are not concerned by the paragraph above.

The burst type, length and latency can be configured. The different configurations for

Synchronous Burst Read operations are described in Section 3.3: Burst Configuration

In Continuous Burst Read, one Burst Read operation can access the entire memory

sequentially by keeping the Burst Address Advance B at VIL for the appropriate number of

clock cycles. At the end of the memory address space the Burst Read restarts from the

beginning at address 000000h.

A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip

Enable and Latch Enable are Low, VIL. The Burst Start Address is latched and loaded into

the internal Burst Address Counter on the valid Burst Clock K edge (rising or falling

depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle (or two clock

cycles depending on the value of M9). The Burst Address Advance B input controls the

memory burst output. The second burst output is on the next clock valid edge after the Burst

Address Advance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst

controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low

on the active clock edge, no new data is available and the memory does not increment the

internal address counter at the active clock edge even if Burst Address Advance, B, is Low.

Table 5.

Asynchronous Read Electronic Signature operation

Code

Device

A18-A0

DQ31-DQ0

Manufacturer

All

VIL

VIH

00000h

00000020h

Device

M58BW016DT

M58BW016FT

VIL

VIH

00001h

00008836h

M58BW016DB

M58BW016FB

VIL

VIH

00001h

00008835h

Burst Configuration

VIL

VIH

00005h

BCR(1)

BCR = Burst Configuration Register.

M58BW016DB 数据表(PDF) 21 Page - STMicroelectronics

M58BW016DB 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载