M58BW016DB datasheet(23/69 Pages) STMICROELECTRONICS

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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

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3.3

Burst Configuration Register

The Burst Configuration Register is used to configure the type of bus access that the

memory will perform.

The Burst Configuration Register is set through the command interface and will retain its

information until it is re-configured, the device is reset, or the device goes into Reset/Power-

down mode. The Burst Configuration Register bits are described in Table 7. They specify the

selection of the burst length, burst type, burst X and Y latencies and the read operation.

Refer to Figure 4 and Figure 5 for examples of synchronous burst configurations.

3.3.1

Read Select bit (M15)

The Read Select bit, M15, is used to switch between Asynchronous and Synchronous Bus

Read operations. When the Read Select bit is set to ’1’, Bus Read operations are

asynchronous; when the Read Select but is set to ’0’, Bus Read operations are

synchronous.

On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.

3.3.2

X-Latency bits (M14-M11)

The X-Latency bits are used during Synchronous Bus Read operations to set the number of

clock cycles between the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 7: Burst

Configuration Register. The X-Latency bits should also be selected in conjunction with

Table 8: Burst type definition to ensure valid settings.

3.3.3

Y-Latency bit (M9)

The Y-Latency bit is used during Synchronous Bus Read operations to set the number of

clock cycles between consecutive reads. The Y-Latency value depends on both the X-

Latency value and the setting in M9.

When the Y-Latency is ‘1’ the data changes each clock cycle; when the Y-Latency is ‘2’ the

data changes every second clock cycle. See Table 7: Burst Configuration Register, and

Table 8: Burst type definition for valid combinations of the Y-Latency, the X-Latency and the

Clock frequency.

3.3.4

Valid Data Ready bit (M8)

The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When

the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the active

clock edge when invalid data is output on the bus. When the Valid Data Ready bit is ’1’ the

Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output

on the bus.

3.3.5

Burst Type bit (M7)

The Burst Type bit is used to configure the sequence of addresses read as sequential or

interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses;

when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Table 8:

Burst type definition, for the sequence of addresses output from a given starting address in

each mode.

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