TUSB1044AI datasheet(21/66 Pages) TI1

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7.3 Feature Description

7.3.1 USB 3.2

The TUSB1044A supports USB 3.2 data rates up to 20Gbps when operating in USB3.2 x2 mode

(USB32_BY2_EN = 1) and up to 10Gbps when operating in USB3.2 x1 mode (USB32_BY2_EN = 0). The

TUSB1044A supports all the USB defined power states (U0, U1, U2, and U3). The TUSB1044A is a linear

redriver, therefore the TUSB1044A cannot decode USB3.2 physical layer traffic. The TUSB1044A monitors the

actual physical layer conditions like receiver termination, electrical idle, LFPS, and SuperSpeed signaling rate to

determine the USB power state of the USB3.2 interface.

The TUSB1044A features an intelligent low-frequency periodic signaling (LFPS) detector. The LFPS detector

automatically senses the low-frequency signals and disables receiver equalization functionality. When not

receiving LFPS, the TUSB1044A enables receiver equalization based on the UEQ[1:0] and DEQ[1:0] pins or

values programmed into UEQ[3:0]_SEL, and DEQ[3:0]_SEL registers.

7.3.2 USB 3.2 x2 Description

The TUSB1044A configured for USB 3.2 x2 mode determines if the link is operating in USB 3.2 x2 or in USB 3.2

x1. If the link is USB 3.2 x2, then TUSB1044A operates with one port operating as a USB 3.2 x1 port and the

remaining port following the lead of the other port. The port functioning as a USB 3.2 x1 port is called the config

lane. The determination of the config lane is based solely on the Type-C orientation. For normal orientation (FLIP

= L), Port 1 is the config lane. For the flipped orientation (FLIP = H), Port 2 is the config lane.

In USB 3.2 x2, the config lane operates as a standard USB 3.2 x1 port. While in all USB low power states

(Disconnect, U1, U2, and U3), the non-config lane is disabled to conserve power. Entry to and exit from these

low power states is determined solely by the config lane. If the config lane detects an exit from a low power

state, then the non-config is enabled.

Table 7-1. Config Lane Selection

DIR0 PIN OR DIR0 REGISTER

FLIP PIN OR FLIP_SEL

CONFIG LANE

NON-CONFIG LANE

0 (source)

DRX1 -> URX1

DRX2 -> URX2

UTX1 -> DTX1

UTX2 -> DTX2

DRX2 -> URX2

DRX1 -> URX1

UTX2 -> DTX2

UTX1 -> DTX1

1 (sink)

DRX2 -> URX2

DRX1 -> URX1

UTX2 -> DTX2

UTX1 -> DTX1

DRX1 -> URX1

DRX2 -> URX2

UTX1 -> DTX1

UTX2 -> DTX2

Note

In GPIO mode the TUSB1044A is enabled for USB3.2 x2 mode when all the following conditions are

true: DIR1 pin = H, DIR0 pin = L or H, CTL0 pin = H and CTL1 pin = H.

In I2C mode, USB3.2 x2 mode is disabled by default. USB3.2x2 in I2C mode is enabled if either of the

following conditions is true:

• At offset 0xA, USB32_BY2_EN bit = 1'b1 and CTLSEL_1:0 bits = 2'b01.

• At offset 0xA, CTLSEL_1:0 bits = 2'b11, and at offset 0xC, DIR_SEL bits = 2'b10 or 2'b11

7.3.3 DisplayPort

The TUSB1044A supports up to four DisplayPort lanes at data rates up to 10.0Gbps (UHBR10). The

TUSB1044A, when configured in DisplayPort mode, monitors the native AUX traffic between the DisplayPort

source and DisplayPort sink. For the purposes of reducing power, the TUSB1044A manages the number

of active DisplayPort lanes based on the content of the AUX transactions. The TUSB1044A snoops native

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TUSB1044A

SLLSG07 – MARCH 2025

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