TUSB1044AI datasheet(4/66 Pages) TI1

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Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

UTX2n

Diff I/O

Differential negative input/output for upstream facing TX2 port.

VIO_SEL

4 Level I/O

This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:

0 = 3.3V configuration I/O voltage, 3.3V I2C interface (Default)

R = 3.3V configuration I/O voltage, 1.8V I2C interface

F = 1.8V configuration I/O voltage, 3.3V I2C interface

1 = 1.8V configuration I/O voltage, 1.8V I2C interface.

UTX1n

Diff I/O

Differential negative input/output for upstream facing TX1 port.

UTX1p

Diff I/O

Differential positive input/output for upstream facing TX1 port.

I2C_EN

4 Level I

I2C Programming or Pin Strap Programming Select.

0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)

R = TI Test Mode (I2C enabled)

F = GPIO Mode, AUX Snoop Disabled (I2C disabled)

1 = I2C enabled.

URX1n

Diff I/O

Differential negative input/output for upstream facing RX1 port.

URX1p

Diff I/O

Differential positive input/output for upstream facing RX1 port.

VCC

3.3V power supply

FLIP/SCL

2 Level I

(PD)

(Failsafe)

In GPIO mode, this is Flip control pin. Otherwise, this pin is I2C clock.

CTL0/SDA

2 Level I

(PD)

(Failsafe)

In GPIO mode, this is a USB3.2 Switch control pin. Otherwise, this pin is I2C data.

CTL1

2 Level I

(PD)

DP Alt mode Switch Control Pin. In GPIO mode, this pin enables or disables the DisplayPort functionality.

Otherwise, DisplayPort functionality is enabled and disabled through I2C registers.

L = DisplayPort Disabled.

H = DisplayPort Enabled.

In I2C Mode, this pin is not used by TUSB1044A.

AUXp

I/O,

CMOS

AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC-coupling

capacitor. In addition to an AC-coupling capacitor, this pin also requires a 100kΩ resistor to GND between

the AC-coupling capacitor and the AUXp pin if the TUSB1044A is used on the DisplayPort source

side, or a 1MΩ resistor to DP_PWR (3.3V) between the AC-coupling capacitor and the AUXp pin if the

TUSB1044A is used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044A

for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.

AUXn

I/O,

CMOS

AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC-coupling

capacitor. In addition to the AC-coupling capacitor, this pin also requires a 100kΩ resistor to DP_PWR

(3.3V) between the AC-coupling capacitor and the AUXn pin if the TUSB1044A is used on the DisplayPort

source side, or a 1MΩ resistor to GND between the AC-coupling capacitor and the AUXn pin if the

TUSB1044A is used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044A

for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C plug.

SBU2

I/O,

CMOS

SBU2. When the TUSB1044A is used on the DisplayPort source side, DC couple this pin to the SBU2 pin

of the Type-C receptacle. When the TUSB1044A is used on the DisplayPort sink side, DC couple this pin

to the SBU1 pin of the Type-C receptacle. A 2MΩ resistor to GND is also recommended.

SBU1

I/O,

CMOS

SBU1. When the TTUSB1044A is used on the DisplayPort source side, DC couple this pin to the SBU1

pin of the Type-C receptacle. When the TUSB1044A is used on the DisplayPort sink side, DC couple this

pin to the SBU2 pin of the Type-C receptacle. A 2MΩ resistor to GND is also recommended.

VCC

3.3V power supply

DEQ1

4 Level I

This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,

DTX1, DTX2 receivers.

DRX1p

Diff I/O

Differential positive input/output for downstream facing RX1 port.

DRX1n

Diff I/O

Differential negative input/output for downstream facing RX1 port.

HPDIN

2 Level I

(PD)

This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater

than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch remains closed. When HPDIN is

high, the enabled DisplayPort lanes from AUX snoop or registers are active.

DTX1p

Diff I/O

Differential positive input/output for downstream facing TX1 port.

DTX1n

Diff I/O

Differential negative input/output for downstream facing TX1 port.

UEQ0/A0

4 Level I

This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,

UTX2 receivers. In I2C mode, this pin also sets the TUSB1044A I2C address. See also Table 7-10.

DTX2n

Diff I/O

Differential negative input/output for downstream facing TX2 port.

DTX2p

Diff I/O

Differential positive input/output for downstream facing TX2 port.

TUSB1044A

SLLSG07 – MARCH 2025

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