TUSB1044AI datasheet(3/66 Pages) TI1

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4 Pin Configuration and Functions

Thermal

Pad

VCC

UEQ1/A1

CFG0

CFG1

SWAP

VCC

SLP_S0#

DIR0

FLIP/SCL

CTL0/SDA

CTL1

AUXp

AUXn

SBU2

SBU1

VCC

Not to scale

Figure 4-1. RNQ Package 40-Pin (WQFN) Top View

Pin Functions

TYPE

DESCRIPTION

NO.

NAME

VCC

3.3V power supply

UEQ1/A1

4 Level I

This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,

UTX2 receivers. In I2C Mode, this pin also sets the TUSB1044A I2C address. See also Table 7-10.

CFG0

4 Level I

CFG0. This pin along with CFG1 selects the VOD linearity range and DC gain for all the downstream and

upstream channels. Refer to Table 7-9 for VOD linearity range and DC gain options.

CFG1

4 Level I

CFG1. This pin along with CFG0 sets the VOD linearity range and DC gain for all the downstream and

upstream channels. Refer to Table 7-9 for VOD linearity range and DC gain options.

SWAP

2 Level I

(PD)

This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data

path inputs.

0 – Do not swap channel directions and EQ settings (Default)

1. – Swap channel directions and EQ settings.

VCC

3.3V power supply

SLP_S0#

2 Level I

(PD)

This pin when asserted low disables the Receiver Detect functionality. While this pin is low and

TUSB1044A is in U2/U3, the TUSB1044A disables the LOS and LFPS detection circuitry and the RX

termination for both channels remains enabled. If this pin is low and the TUSB1044A is in the disconnect

state, the RX detect functionality is disabled and RX termination for both channels is disabled.

0 – RX Detect disabled

1 – RX Detect enabled (Default)

DIR0

2 Level I

(PD)

This pin along with DIR1 sets the data path signal direction format. Refer to Table 7-5 for signal direction

formats.

0 - Source Side (DFP) Alt Mode format

1 - Sink Side (UFP) Alt Mode format

URX2p

Diff I/O

Differential positive input/output for upstream facing RX2 port.

URX2n

Diff I/O

Differential negative input/output for upstream facing RX2 port.

DIR1

2 Level I/O

(PD)

This pin along with DIR0 sets the data path signal direction format. Refer to Table 7-5 for signal direction

formats.

0 - DisplayPort Alt Mode format

1 - Custom Alt Mode format

UTX2p

Diff I/O

Differential positive input/output for upstream facing TX2 port.

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TUSB1044A

SLLSG07 – MARCH 2025

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