ADIN1111BCPZ-R7 datasheet(39/109 Pages) AD

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Data Sheet

ADIN1111

MAC SPI

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Rev. A | 39 of 109

Receive Data Footer

Table 37. Receive Data Footer

D31

D30

D29

D28 to D24

D23 to D22

D21

D20

D19 to D16

D15

D14

D13 to D8

D5 to D1

EXST

HDRB

SYNC

RCA

SWO

EBO

RTSA

RTSP

TXC

See the following definitions:

►

EXST: extended status. This bit is set when any bit in the

STATUS0 or STATUS1 registers are set and not masked.

►

HDRB: received header bad. When this bit is set, the MAC-PHY

has received a control or data header with a parity error.

►

SYNC: configuration synchronized flag. This field reflects the

state of the SYNC bit in the CONFIG0 register. When 0, this

bit indicates that the MAC-PHY configuration may not be as

expected by the SPI host. Following configuration, the SPI host

sets the corresponding bit in the configuration register, which is

reflected in this field.

►

RCA: receive chunks available. The RCA field indicates the

minimum number of additional receive data chunks of frame data

that are available for reading beyond the current one. This field is

0 when there is no more receive frame data pending in the buffer

of the MAC-PHY to be read.

►

VS: vendor specific.

►

VS[1]: priority of the received frame.

►

0: frame received via the low priority queue.

►

1: frame received via the high priority queue.

►

VS[0]: reserved.

►

DV: data valid flag. The SPI host uses this bit to indicate if the

current chunk contains valid transmit data (DV = 1) or not. When

this bit is 0, the SPI host ignores the chunk payload.

►

SV: start valid flag. When this bit is 1, the beginning of an

Ethernet frame is present in the current transmit data chunk

payload. The SV bit is not to be confused with the SFD byte

described in IEEE Standard 802.3.

►

SWO: start word offset. When SV is 1, this field contains the

32-bit word offset into the receive data chunk payload that points

to the start of the new Ethernet frame. When a receive time

stamp is added to the beginning of the received frame (RTSA =

1), SWO points to the most significant byte of the time stamp. If

SV is 0, the host must write this field as 0.

►

FD: frame drop. When set, this bit indicates that the MAC has

detected a condition for which the SPI host must drop the

received Ethernet frame. This bit is only valid at the end of a

received frame (EV = 1), and must be 0 at all other times.

►

EV: end valid flag. When this bit is 1, the end of an Ethernet

frame is present in the current receive data chunk payload.

►

EBO: end byte offset. When EV is 1, this field contains the byte

offset into the receive data chunk payload that points to the last

byte of the received Ethernet frame. This field is 0 when EV = 0.

►

RTSA: receive time stamp added. This bit is set when a 32-bit

or 64-bit time stamp is added to the beginning of the SPI frame.

This bit must be 0 when SV = 0.

►

TXC: transmit credits. This field contains the minimum number of

transmit data chunks of frame data that the SPI host can write in

a single transaction without incurring a transmit buffer overflow.

►

P: parity. Parity bit calculated over the receive data header.

Method is odd parity.

OPEN Alliance SPI Cut Through Mode

If cut through from or to the host is enabled, the method to transfer

frames remains the same as when using store and forward mode.

However, the frame receive starts when sufficient frame data to fill a

chunk is received, and the frame transmit starts when a configured

transmit threshold is reached (see the Transmit Threshold Register

section).

The cut through mode can be enabled via the receive cut through

enable bits and transmit cut through enable bits (see the Configura-

tion Register 0 section).

On receive, the MAC returns data as it becomes available. Unlike

in store and forward mode, there may be empty chunks (DV = 0)

between a start of frame (SOF) chunk and an end of frame (EOF)

chunk.

If the host does not read frames fast enough to keep the receive

FIFO empty, the frames are then buffered in the receive FIFO as if

it is operating in store and forward mode. When all the frames are

read, the FIFO returns to operating in cut through mode.

On transmit, the host must provide frame data at a rate fast

enough (>10 Mbps) to ensure that the frame does not under run on

transmit. If the MAC under runs, TXBUE in the STATUS0 register

asserts and the MAC stops transmitting the frame in progress and

appends a bad CRC to the frame.

Cut Through Transmit Latency

The time interval between the time the start of an SPI data transac-

tion with a transmit header SWO of 0 (frame starts immediately

in the chunk), and the time TX_EN rises on the MII with an SPI

frequency of 16 MHz and TX_THRESH = 1 is 4 μs. The PHY

transmit latency is 3.2 μs. This makes a total transmit latency of 7.2

μs.

Cut Through Receive Latency

The receive latency varies based on the chunk size and the SPI

frequency. Table 38 indicates the latency for an SPI frequency of 16

MHz and all supported chunk sizes.

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