ADIN1111BCPZ-R7 datasheet(13/109 Pages) AD

13 / 109 page

Data Sheet

ADIN1111

THEORY OF OPERATION

analog.com

Rev. A | 13 of 109

►

Non APL: >160 µH differentially to achieve approximately 25%

max droop.

►

Recommended >47 µH coupled inductor (two inductors on

a common magnetic core).

►

Or two >100 µH individual inductors.

Note that an isolation transformer is present on the MDI transmis-

sion line, the parallel combination between the inductance of the

transformer and the total differential inductance of the power induc-

tor must be greater than 160 µH.

Figure 10. Typical MDI Circuitry with Capacitive Coupling for the ADIN1111

Figure 11. Typical MDI Circuitry with Galvanic Isolation for the ADIN1111

Figure 12. Typical MDI Circuitry with Power Coupling for the ADIN1111

RESET OPERATION

The ADIN1111 supports the following chip resets:

►

Power-on reset

►

Hardware reset

►

Software reset

►

MAC subsystem reset

►

PHY subsystem reset

All of these resets put the ADIN1111, including the PHY core and

MAC, into a known state. Whenever the MAC is reset, the SDO pin

is pulled down and the TS_TIMER pin is driven to a low state.

Power-On Reset

The ADIN1111 includes power monitoring circuitry to monitor all of

the supplies. During power-up, the ADIN1111 is held in hardware

reset until each of the supplies has crossed its minimum rising

threshold value and the power is considered good.

The POR module includes brownout protection by monitoring the

supplies to detect if one or more of the supplies falls below a

minimum falling threshold value. If brownout detection occurs, the

device is held in hardware reset until the power is good.

Hardware Reset

A hardware reset is initiated by the power-on reset circuitry or

by asserting the RESET pin low. Bring the RESET pin low for a

minimum of 10 µs. Deglitch circuitry is included on this pin to reject

pulses shorter than 0.3 μs.

When the RESET pin is deasserted, all the input/output (I/O) pins

are held in tristate mode, the hardware configuration pins are latch-

ed, and the I/O pins are configured for their functional mode. When

all the external and internal supplies are valid and stable, the crystal

oscillator circuit is enabled. After the crystal starts up and stabilizes,

the phase-locked loop PLL is enabled. After approximately 50 ms

(maximum) from the deassertion of the RESET pin, all the internal

clocks are valid, internal logic is released from reset, and all the

management interface registers are accessible so that the device

can be programmed.

Software Reset

A full chip software reset can be initiated by writing 1 to the

SWRESET field of the RESET register.

If a transmission is taking place when the SPI software reset is initi-

ated, the frame transmission stops abruptly and a runt or a frame

with a bad cyclic redundancy check (CRC) may be transmitted.

Once the MAC-PHY is reset, the ADIN1111 is ready to bring up

links.

When this software reset is initiated, a full initialization of the chip,

almost equivalent to a hardware reset, is done. The I/O pins are

held in tristate mode, the hardware configuration pins are latched,

and the I/O pins are configured for their functional mode. The crys-

tal oscillator circuit is enabled, and after the crystal starts up and

stabilizes, the PLL is enabled. Approximately 10 ms (maximum)

after writing the SOFT_RST keys, the internal logic is released from

reset and all the management interface registers are accessible.

MAC Subsystem Reset

A MAC only software reset is initiated by writing the required pair of

keys to the SOFT_RST register.

The reset is applied for about 1.2 µs. The MAC subsystem reset

interrupts any transmit/receive packet exchange between the MAC

and the PHY, but does not drop any existing link nor prevents

a link from establishing. The PHY management registers are not

initialized.

The PHY needs to be out of software power-down to trigger a MAC

only software reset.

ADIN1111BCPZ-R7 数据表(PDF) 13 Page - Analog Devices

ADIN1111BCPZ-R7 数据表(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载