Data Sheet

ADP1763

APPLICATIONS INFORMATION

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Rev. E | 15 of 22

CAPACITOR SELECTION

Output Capacitor

The ADP1763 is designed for operation with small, space-saving

ceramic capacitors, but it can function with most commonly used

capacitors as long as care is taken with the effective series resist-

ance (ESR) value. The ESR of the output capacitor affects the

stability of the LDO control loop. A minimum of 10 µF capacitance

with an ESR of 500 mΩ or less is recommended to ensure the

stability of the ADP1763. Transient response to changes in load

current is also affected by output capacitance. Using a larger

value of output capacitance improves the transient response of the

ADP1763 to large changes in load current. Figure 31 and Figure 32

show the transient responses for output capacitance values of 10

µF and 47 µF, respectively.

Figure 31. Output Transient Response, COUT = 10 µF

Figure 32. Output Transient Response, COUT = 47 µF

Input Bypass Capacitor

Connecting a 10 µF capacitor from the VIN pin to the GND pin

to ground reduces the circuit sensitivity to the PCB layout, especial-

ly when long input traces or a high source impedance is encoun-

tered. If output capacitance greater than 10 µF is required, it is

recommended that the input capacitor be increased to match it.

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP1763, as

long as they meet the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a voltage

rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics

are not recommended, due to their poor temperature and dc bias

characteristics.

Figure 33 shows the capacitance vs. bias voltage characteristics of

an 0805 case, 10 µF, 10 V, X5R capacitor. The voltage stability of

a capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or with a higher

voltage rating exhibits better stability. The temperature variation

of the X5R dielectric is about ±15% over the −40°C to +85°C

temperature range and is not a function of package size or voltage

rating.

Figure 33. Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst case capacitance, account-

ing for capacitor variation over temperature, component tolerance,

and voltage.

CEFF=COUT× 1−tempco × 1−TOL (4)

where:

CEFF is the effective capacitance at the operating voltage.

COUT is the output capacitor.

Tempco is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst case temperature coefficient (tempco)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.