Data Sheet

ADA4352-2

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Rev 0

41 of 47

Using the ADA4352-2 LTspice Model

Figure 83 shows the available LTspice model for the ADA4352-2 used to generate many of the parametric and Monte

Carlo curves shown in this applications section.

Figure 83. ADA4352-2 LTspice Model Setup for the Swept CD Curves Using the 315 Ω Gain Setting

The example simulation of Figure 83 is set up for a stepped CD plot similar to that in Figure 79 using the lowest gain

setting of 315 Ω. Consider these configurations in any application simulation:

1. Set the PGTIA power supplies, AVDD = 5 V and AVSS = ground, here for single supply operation.

2. Set the DC bias on the +IN pin. This must be at least 0.1 V higher than AVSS and 1.5 V below AVDD for proper

operation. Here, a 0.5 V bias is used. The polarity of the diode current (I1) guarantees that the output only

increases from that 0.5 V level.

3. Set values for desired photodiode equivalent model parameters, such as source capacitance (C2 here) at

desired reverse bias voltage, and parasitic shunt resistance (not shown in Figure 83) at the maximum

intended operating temperature.

4. The digital switch control inputs, SW SEL0 and SW SEL1, must be set for the desired gain setting, as

detailed in Figure 83. Usually, these control voltages are set to either 0 V at DVSS for a logic 0 or to the

digital supply voltage DVDD (V3 here) for a logic 1.

5.

There is usually an external RC filter after the PGTIA output to the SAR ADC. The values here come from the

16-bit 1 MSPS SAR AD4696 data sheet.

Error Budget

The input offset error of the ADA4352-2 is constant across all gain settings because TIA noise gain is approximately

1 for all gain ranges. This simplifies the error budget because most DC error terms due to the PGTIA are combined

in Output Offset Voltage (VOS,OUT). This term is a result of three components: the switch off leakage current (IOFF),

input bias current of the inverting input, and offset voltage of the core amplifier. The only other source of error is

the effect of noninverting input bias current flowing through the source impedance at the noninverting input.

The following equation shows the “Total Output DC Offset Error” at room temperature.

OUT

R2

200Ω

C1

180pF

V4

0

V5

0

V3

3.3

PGTIAOUT

SWSEL0

SWSEL1

DIGITAL

SUPPLY

SWITCH SETTINGS

SWSEL0 = 0, SWSEL1 = 0 RF0 = 315Ω

SWSEL0 = 1, SWSEL1 = 0 RF1 = 3500Ω

SWSEL0 = 0, SWSEL1 = 1, RF2 = 40.2kΩ

SWSEL0 = 1, SWSEL1 = 1, RF3 = 450kΩ

4.4MHz LOW PASS FILTER

ADCIN

DVDD

DVSS

SW SEL0

SW SEL1

–IN

I1

+IN

AVDD

VDD

5

VSS

0

X1

AVSS

ada4352_gb

C2

{Cd}

.step param Cd 5p 45p 5p

.ac dec 50 10k 10M

0

AC 1

VBIAS

0.5

7pF

2.5pF

33pF

26.5pF

RF2 = 40.2kΩ

RF3 = 450kΩ

RF0 = 315Ω

RF1 = 3.5kΩ