ADBMS1818ASWZ-R7 datasheet(34/92 Pages) AD

34 / 92 page

Data Sheet

ADBMS1818

THEORY OF OPERATION

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Rev. B | 34 of 92

Sum of All Cells Measurement

The sum of all cells (SC) measurement is the voltage between C18

and C0 with a 30:1 attenuation. The 16-bit ADC value of sum of

all cells measurement is stored in Status Register Group A. Any

potential difference between the C0 and V– pins results in an error

in the SC measurement equal to this difference. From the SC value,

the sum of all cell voltage measurements is given by:

Sum of all cells = SC × 30 × 100 µV

Internal Die Temperature Measurement

The ADSTAT command can measure the internal die temperature

(ITMP). The 16-bit ADC value of the ITMP is stored in Status Regis-

ter Group A. From ITMP, the actual die temperature is calculated

using the expression:

Internal Die Temperature (°C) =

ITMP× 100μV7.6mV

°C − 276°C

Power Supply Measurements

The ADSTAT command is also used to measure the analog power

supply (VREG) and digital power supply (VREGD). The 16-bit ADC

value of the analog power supply measurement (VA) is stored in

Status Register Group A. The 16-bit ADC value of the digital power

supply measurement (VD) is stored in Status Register Group B.

From VA and VD, the power supply measurements are given by:

Analog power supply measurement (VREG) = VA × 100 µV

Digital power supply measurement (VREGD) = VD × 100 µV

The value of VREG is determined by external components. VREG

must be between 4.5 V and 5.5 V to maintain accuracy. The value

of VREGD is determined by internal components. The normal range

of VREGD is 2.7 V to 3.6 V.

Measuring Internal Device Parameters with

Digital Redundancy (ADSTATD Command)

The ADSTATD command operates similarly to the ADSTAT com-

mand except that an additional diagnostic is performed using digital

redundancy. PS, Bits[1:0] in Configuration Register Group B must

be set to 0 or 1 during the ADSTATD command to enable redun-

dancy. See the ADC Conversion with Digital Redundancy section.

The execution time of the ADSTAT command and the ADSTATD

command is the same.

ADC Conversion with Digital Redundancy

Each of the three internal ADCs contains its own digital integra-

tion and differentiation machine. The ADBMS1818 also contains a

fourth digital integration and differentiation machine that is used for

redundancy and error checking.

All of the ADC and self test commands, except ADAX and ADSTAT,

can operate with digital redundancy. This includes ADCV, ADOW,

CVST, ADOL, ADAXD, AXOW, AXST, ADSTATD, STATST, ADC-

VAX, and ADCVSC. When performing an ADC conversion with

redundancy, the analog modulator sends its bit stream to both

the primary digital machine and the redundant digital machine. At

the end of the conversion, the results from the two machines are

compared. If any mismatch occurs, a value of 0xFF0X (≥6.528 V)

is written to the result register. This value is outside of the clamping

range of the ADC and the host identifies this as a fault indication.

The last four bits are used to indicate which nibble(s) of the result

values did not match.

Table 26. Indication of Digital Redundancy Fault Bit Location

Result

Indication

0b1111_1111_0000_0XXX

No fault detected in Bit 15 to Bit 12

0b1111_1111_0000_1XXX

Fault detected in Bit 15 to Bit 12

0b1111_1111_0000_X0XX

No fault detected in Bit 11 to Bit 8

0b1111_1111_0000_X1XX

Fault detected in Bit 11 to Bit 8

0b1111_1111_0000_XX0X

No fault detected in Bit 7 to Bit 4

0b1111_1111_0000_XX1X

Fault detected in Bit 7 to Bit 4

0b1111_1111_0000_XXX0

No fault detected in Bit 3 to Bit 0

0b1111_1111_0000_XXX1

Fault detected in Bit 3 to Bit 0

Because there is a single redundant digital machine, the machine

can apply redundancy to only one ADC at a time. By default,

the ADBMS1818 automatically selects the ADC path redundancy.

However, the user can choose an ADC redundancy path selection

by writing to the PS, Bits[1:0] in Configuration Register Group B.

Table 27 shows all possible ADC path redundancy selections.

When the FDRF bit in Configuration Register Group B is written to

1, this bit forces the digital redundancy comparison to fail during

subsequent ADC conversions.

Measuring Cell Voltages and Sum of All Cells

(ADCVSC Command)

The ADCVSC command combines 18 cell measurements and

the sum of all cells measurement. This command simplifies the

synchronization of the individual battery cell voltage and the total

sum of all cells measurements. Figure 60 shows the timing of the

ADCVSC command. See the Commands section for the ADCVSC

command format. The synchronization of the cell voltage and sum

of all cells measurements, tSKEW, in fast mode is within 147 μs.

Table 28 shows the conversion and synchronization time for the

ADCVSC command in different modes. The total conversion time

for the command is given by t7C.

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