ADBMS1818ASWZ-R7 datasheet(75/92 Pages) AD

75 / 92 page

Data Sheet

ADBMS1818

APPLICATIONS INFORMATION

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Rev. B | 75 of 92

CELL BALANCING

Cell Balancing with Internal MOSFETs

With passive balancing, if one cell in a series stack becomes over-

charged, an S output can slowly discharge this cell by connecting it

to a resistor. Each S output is connected to an internal N-channel

MOSFET with a maximum on resistance of 10 Ω. An external

resistor must be connected in series with these MOSFETs to allow

most of the heat to be dissipated outside of the ADBMS1818

package, as shown in Figure 99.

The internal discharge switches (MOSFETs) S1 through S18 can

be used to passively balance cells as shown in Figure 99 with

balancing current of 200 mA or less (80 mA or less if the die

temperature is over 85°C). Balancing current larger than 200 mA

is not recommended for the internal switches due to excessive

die heating. When discharging cells with the internal discharge

switches, the die temperature must be monitored. See the Thermal

Shutdown section.

Note that the antialiasing filter resistor is part of the discharge path

and must be removed or reduced. Use of an RC for added cell

voltage measurement filtering is permitted, but the filter resistor

must remain small, typically around 10 Ω to reduce the effect on the

balance current.

Figure 99. Internal/External Discharge Circuits

Cell Balancing with External Transistors

For applications that require balancing currents above 200 mA or

large cell filters, the S outputs can be used to control external

transistors. The ADBMS1818 includes an internal pull-up PMOS

transistor with a 1 kΩ series resistor. The S pins can act as digital

outputs suitable for driving the gate of an external MOSFET, as

shown in Figure 99. Figure 96 shows external MOSFET circuits that

include RC filtering. For applications with very low cell voltages, the

PMOS in Figure 99 can be replaced with a PNP. When a PNP is

used, the resistor in series with the base must be reduced.

Choosing a Discharge Resistor

When sizing the balancing resistor, it is important to know the

typical battery imbalance and the allowable time for cell balancing.

In most small battery applications, it is reasonable for the balancing

circuitry to be able to correct for a 5% state of charge (SOC) error

with 5 hours of balancing. For example, a 5 AHr battery with a 5%

SOC imbalance has approximately 250 mA Hrs of imbalance. Using

a 50 mA balancing current, the error can be corrected in 5 hours.

With a 100 mA balancing current, the error can be corrected in 2.5

hours. In systems with very large batteries, it is difficult to use pas-

sive balancing to correct large SOC imbalances in short periods of

time. The excessive heat created during balancing generally limits

the balancing current. In large capacity battery applications, if short

balancing times are required, an active balancing solution must

be considered. When choosing a balance resistor, the following

equations can be used to help determine a resistor value:

Balance Current =

% of SOC Imbalance×Battery Capacity

Number of Hours to Balance

Balance Resistor =

Nominal Cell Voltage

Balance Current

Active Cell Balancing

Applications that require 1 A or greater of cell balancing current

must consider implementing an active balancing system. Active

balancing allows for much higher balancing currents without the

generation of excessive heat. Active balancing also allows for ener-

gy recovery since most of the balance current is redistributed back

to the battery pack. Figure 100 shows a simple active balancing

implementation using the LT8584. The LT8584 also has advanced

features that can be controlled via the ADBMS1818. See the S Pin

Pulsing Using the S Pin Control Settings section and the LT8584

data sheet for more details.

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