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ADBMS1818ASWZ-R7 数据表(PDF) 9 Page - Analog Devices |
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ADBMS1818ASWZ-R7 数据表(HTML) 9 Page - Analog Devices |
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9 / 92 page ![]() Data Sheet ADBMS1818 SPECIFICATIONS analog.com Rev. B | 9 of 92 ISOSPI IDLE/WAKE-UP SPECIFICATIONS See Figure 87. Table 7. Parameter Test Conditions/Comments Min Typ Max Unit Differential Wake-Up Voltage (VWAKE) Dwell time at VWAKE before wake detection (tDWELL) = 240 ns, apply over the full specified temperature range 200 mV tDWELL VWAKE = 200 mV, apply over the full specified temperature range 240 ns Start-Up Time After Wake Detection (tREADY) Apply over the full specified temperature range 10 µs Idle Timeout Duration (tIDLE) Apply over the full specified temperature range 4.3 5.5 6.7 ms ISOSPI PULSE TIMING SPECIFICATIONS See Figure 83. Table 8. Parameter Test Conditions/Comments Min Typ Max Unit Chip Select Half Pulse Width (t1/2PW(CS)) Transmitter, apply over the full specified temperature range 120 150 180 ns Chip Select Signal Filter (tFILT(CS)) Receiver, apply over the full specified temperature range 70 90 110 ns Chip Select Pulse Inversion Delay (tINV(CS)) Transmitter, apply over the full specified temperature range 120 155 190 ns Chip Select Valid Pulse Window (tWNDW(CS)) Receiver, apply over the full specified temperature range 220 270 330 ns Data Half Pulse Width (t1/2PW(D)) Transmitter, apply over the full specified temperature range 40 50 60 ns Data Signal Filter (tFILT(D)) Receiver, apply over the full specified temperature range 10 25 35 ns Data Pulse Inversion Delay (tINV(D)) Transmitter, apply over the full specified temperature range 40 55 65 ns Data Valid Pulse Window (tWNDW(D)) Receiver, apply over the full specified temperature range 70 90 110 ns SPI TIMING REQUIREMENTS See Figure 77 and Figure 86. Table 9. Parameter Test Conditions/Comments Min Typ Max Units SCK Period (tCLK)1 Apply over the full specified temperature range 1 µs SDI Setup Time Before SCK Rising Edge (t1) Apply over the full specified temperature range 25 ns SDI Hold Time After SCK Rising Edge (t2) d Apply over the full specified temperature range 25 ns SCK Low (t3) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature range 200 ns SCK High (t4) tCLK = t3 + t4 ≥ 1 µs, apply over the full specified temperature range 200 ns CSB Rising Edge to CSB Falling Edge (t5) Apply over the full specified temperature range 0.65 µs SCK Rising Edge to CSB Rising Edge (t6) 1 Apply over the full specified temperature range 0.8 µs CSB Falling Edge to SCK Rising Edge (t7) 1 Apply over the full specified temperature range 1 µs 1 These timing specifications are dependent on the delay through the cable and include allowances for 50 ns of delay in each direction. 50 ns corresponds to 10 m of Category 5 (CAT-5) cable (which has a velocity of propagation of 66% the speed of light). Using longer cables requires derating these specs by the amount of additional delay. |
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