ADE9103 datasheet(49/55 Pages) AD

49 / 55 page

Data Sheet

ADE9103/ADE9112/ADE9113

analog.com

Rev. A | 49 of 55

Table 20. Register Details

Addr

Name

Bits Bit Name

Settings Description

Reset Access

0x001

SWRST

[7:0] SWRST

Software Reset.

0x0

0xD6

Software Reset Command. The software resets all registers to

their default values. Power cycling the device may be required to

correct hardware functionality.

0x002

CONFIG0

[7:4] RESERVED

Reserved.

0x0

[3:2] STREAM_DBG

Stream Debug. Stream debug mode allows configuration of the

x_WAV_x ADC output registers to simplify the debugging of the

communication interface.

0x0

R/W

Normal Mode. The x_WAV_x registers contain the ADC results.

Static Mode. The x_WAV_x registers are static and hold their

value. The x_WAV_x registers can be written to change to a new

value. The x_WAV_x registers become static and hold their value

until a register write is performed to the x_WAV_x register with

a new value. Programming must first be enabled with the count

mode. setting before this static mode functions.

Count Mode. Data Increments at ADC Conversion Rate. Enables

write access to x_WAV_x registers and increments the x_WAV_x

Reserved. Same operation as normal mode.

CRC_EN_SPI_WRITE

Enables CRC Check on SPI Writes.

0x1

R/W

CLKOUT_EN

CLKOUT Enable. Set this bit to 1 to enable CLKOUT when the

device is providing the clock to the remaining ADE9103/ADE9112/

ADE9113 devices. Clear this bit to 0 if receiving an external clock,

in which case, the pin is DREADY.

0x0

R/W

0x003

CONFIG_FILT

RESERVED

Reserved.

0x0

V2_ADC_INVERT

Invert V2 Channel Inputs. The invert bit can be used to correct for

a sensor output connected up backwards.

0x0

R/W

V1_ADC_INVERT

Invert V1 Channel Inputs. See the V2_ADC_INVERT description.

0x0

R/W

I_ADC_INVERT

Invert Current Channel Inputs. See the V2_ADC_INVERT

description.

0x0

R/W

LPF_BW

Filter Bandwidth Configuration. Selects the bandwidth of the digital

LPF of the ADC. See the Analog-to-Digital Conversion section for

details on how the ADC output frequency influences the bandwidth

selection.

0x0

R/W

Bandwidth of 2.7 kHz at 8 kSPS output data rate.

Bandwidth of 3.3 kHz at 8 kSPS output data rate.

[2:0] DATAPATH_CONFIG

Digital Signal Processing Configuration.

0x0

R/W

000

Sinc3, 32 kHz Sampling.

001

Sinc3, LPF Enabled, 32 kHz Sampling.

010

Sinc3, Compensation Enabled, LPF Enabled, 32 kHz Sampling.

011

Sinc3, LPF Enabled, 8 kHz Sampling.

100

Sinc3, Compensation Enabled, LPF Enabled, 8 kHz Sampling.

101

Sinc3, LPF Enabled, 4 kHz Sampling.

110

Sinc3, LPF Enabled, 2 kHz Sampling.

111

Sinc3, LPF Enabled, 1 kHz Sampling.

0x005

CONFIG_ISO_ACC

[7:1] RESERVED

Reserved.

0x0

ISO_WR_ACC_EN

Enable Write Access to DC_OFFSET_MODE Register.

0x0

R/W

0x006

CRC_RESULT_HI

[7:0] CRC_RESULT[15:8]

0xDD R

0x007

CRC_RESULT_LO

[7:0] CRC_RESULT[7:0]

0x8D R

0x008

EFUSE_REFRESH

[7:1] RESERVED

Reserved.

0x0

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