ADE9103 datasheet(24/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

THEORY OF OPERATION

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Rev. A | 24 of 55

ANALOG INPUTS

The ADE9113 has three analog inputs: one current channel and

two voltage channels. The ADE9112 does not include the second

voltage channel. The current channel has two fully differential

voltage input pins, IP and IM, that accept a maximum differential

signal of ±31.25 mV.

The maximum IP voltage (VIP) signal level is also ±31.25 mV. The

maximum IM voltage (VIM) signal level allowed at the IM input is

±25 mV. Figure 30 shows a schematic of the input for the current

channel and the relation to the maximum IM pin voltage.

Figure 30. Maximum Input Level, Current Channel

Note that the current channel senses the voltage across a shunt.

In this case, one pole of the shunt becomes the ground of the

meter (see Figure 35) and, therefore, the current channel is used

in a pseudo differential configuration, similar to the voltage channel

configuration (see Figure 31).

The V1 and V2 voltage channels are fully differential, but most typi-

cally used in a pseudo differential setup. These differential voltage

inputs have a maximum input voltage of ±1000 mV. If setup pseudo

differentially, the voltage inputs have a maximum input voltage of

±500 mV with respect to V1M or V2M. The maximum signal allowed

on the VxP or VxM pins is ±600 mV. Figure 31 shows a schematic

of the voltage channel inputs and their relation to the maximum

VxM voltage.

Figure 31. Maximum Input Level, Voltage Channels

ANALOG-TO-DIGITAL CONVERSION

The ADE9103/ADE9112/ADE9113 have three, second-order, multi-

bit Σ-Δ ADCs. For simplicity, the block diagram in Figure 32 shows

a first-order Σ-Δ ADC. The converter is composed of the Σ-Δ

modulator and the digital low-pass filter (LPF), separated by the

digital isolation block.

Figure 32. First-Order Σ-Δ ADC

A Σ-Δ modulator converts the input signal into a continuous serial

stream of 1s and 0s at a rate determined by the sampling clock.

In the ADE9103/ADE9112/ADE9113, the sampling clock is equal

to XTALIN/16 (1.024 MHz when XTALIN = 16.384 MHz). The 1-bit

DAC in the feedback loop is driven by the serial stream. The DAC

output is subtracted from the input signal. If the loop gain is high

enough, the average value of the DAC output (and, therefore, the

bit stream) can approach that of the input signal level. For any

given input value in a single sampling interval, the data from the

1-bit ADC is virtually meaningless. A meaningful result is obtained

only when a large number of samples is averaged. This averaging

is completed in the second part of the ADC, the digital LPF, after

the data passes through the digital isolators. By averaging a large

number of bits from the modulator, the LPF can produce 24-bit

data-words that are proportional to the input signal level.

The Σ-Δ converter uses two techniques to achieve high resolution

from what is essentially a 1-bit conversion technique. The first

technique is oversampling. Oversampling means that the signal

is sampled at a rate (frequency) that is many times higher than

the bandwidth of interest. For example, when XTALIN = 16.384

MHz, the sampling rate in the ADE9103/ADE9112/ADE9113 is

1.024 MHz, and the bandwidth of interest is 40 Hz to 3.3 kHz.

Oversampling has the effect of spreading the quantization noise

(noise due to sampling) over a wider bandwidth. With the noise

spread more thinly over a wider bandwidth, the quantization noise

in the bandwidth of interest is lowered, as shown in Figure 33.

However, oversampling alone is not sufficient to improve the SNR

in the band of interest. For example, an oversampling factor of

4 is required to increase the SNR by a mere 6 dB (1 bit). To

keep the oversampling ratio at a reasonable level, it is possible to

shape the quantization noise so that the majority of the noise lies

at the higher frequencies. Noise shaping is the second technique

that achieves high resolution. In the Σ-Δ modulator, the noise is

shaped by the integrator, which has a high-pass type response for

the quantization noise. The result is that most of the noise is at the

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