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Data Sheet

ADE9103/ADE9112/ADE9113

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. A | 17 of 55

Table 12. ADE9112 and ADE9113 Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

ADE9112

ADE9113

CLKOUT/DREADY

Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple

ADE9103/ADE9112/ADE9113 Devices section for details), the ADE9112 and ADE9113 generate

a digital signal synchronous to the main clock at the XTALIN pin. Use CLKOUT to provide

a clock to the other ADE9112 and ADE9113 devices on the board. Data Ready, Active Low

(DREADY). When DREADY functionality is selected (see the Synchronizing Multiple ADE9103/

ADE9112/ADE9113 Devices section for details), the ADE9112 and ADE9113 generate an active

low signal synchronous to the ADC output frequency. Use this signal to start reading the ADC

outputs of the ADE9112 and ADE9113.

18, 25

DGND

Ground Reference.

MOSI

Data Input for the SPI Port.

MISO

Data Output for the SPI Port. Attach a 10 kΩ pull-up resistor to the VDD supply voltage for

increased EMC robustness.

SCLK

Serial Clock Input for the SPI Port. All serial data transfers are synchronized to this clock (see

Table 3 for SPI interface timing parameters and SPI Compatible Communication section for

additional SPI port details).

Chip Select for SPI Port (Active Low).

VLDOOUT

1.8 V Output of Digital LDO Regulator. Decouple the VLDOOUT pin with a 4.7 µF capacitor in

parallel with a ceramic 100 nF capacitor to DGND, Pin 25. Do not connect the external load

circuitry to the VLDOOUT pin.

VDD

Primary Supply Voltage. The VDD pin provides the supply voltage for the and ADE9113. Maintain

the supply voltage at 3.3 V ± 10% for specified operation. Decouple the VDD pin to DGND, Pin

25, with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor.

XTALOUT

Crystal Output. A crystal must be chosen based on the transconductance (gm) in Table 2.The

crystal is connected across the XTALIN and XTALOUT pins to provide a clock source for the

ADE9112 and ADE9113. The XTALOUT pin must float when unused.

XTALIN

Main Clock Input. An external clock can be provided at this logic input. The CLKOUT signal of

another appropriately configured ADE9103/ADE9112/ADE9113 (see the Synchronizing Multiple

ADE9103/ADE9112/ADE9113 Devices section for details) can be provided at the XTALIN pin.

Alternatively, a crystal can be connected across the XTALIN and XTALOUT pins to provide a

clock source for the ADE9112 and ADE9113. See the Crystal Oscillator/External Clock section for

more details.

RESET

Active Low Reset Input. To initiate a hardware reset, the RESET pin must be brought low for a

minimum of 1.5 μs.

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