ADE9112 datasheet(42/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

APPLICATIONS INFORMATION

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SPI Debug Features

The ADE9103/ADE9112/ADE9113 has two modes to aid in debug-

ging the SPI communication: static and count mode. The two

modes can be enabled by writing to Bits[3:2], STREAM_DBG, in

the CONFIG0 register. In static mode, the ADC registers become

static and hold their value until they are written to. The register

values can be read as usual through either short or long SPI

transactions. To write and hold a value to the ADC registers, take

the following steps:

1. Set STREAM_DBG equal to count mode (10b).

2. Wait for DREADY.

3. Write the desired values to the ADC register before the next

DREADY.

4. Set STREAM_DBG equal to static mode (01b).

By outputting a known ADC value with every transaction, a user

can verify that the data is being transmitted properly.

The count mode increments the values inside the ADC registers

at the ADC conversion rate that is configured in Bits[2:0], DATA-

PATH_CONFIG, in the CONFIG_FILT register. This mode allows a

user to verify their waveform streaming interface. By verifying that

the read count is unbroken, the user can be assured that no data

has been missed or duplicated. When entering count mode, the

incrementing starts from the last value in the ADC registers. To

enter count mode at a specific value, take the following steps:

1. Set STREAM_DBG equal to count mode (10b).

2. Wait for DREADY.

3. Write the desired values to the ADC register before the next

DREADY.

4. On each following DREADY trigger, the ADC register values

increment.

To exit either debug mode, set STREAM_DBG to normal mode.

Table 16. STREAM_DBG Bit Configuration

STREAM_DBG

Data Mode

Normal mode

Static mode

Count mode

CRC of Command Packet

The 8-bit CRC required in the command packet is calculated over

Bits[31:8], has a polynomial of 0x7 as follows, an initial value of

0x0, and a final XOR of 0x55:

x8 + x2 + x +1

For example, a write command to disable the

CRC_EN_SPI_WRITE bit in the CONFIG0 register sends the fol-

lowing data on the MOSI line: 0x40 02 00 F9, where 0xF9 is the

CRC.

The ADE9103/ADE9112/ADE9113 calculates the CRC after every

calculation to verify successful communication. If the calculated

CRC does not match the received CRC, the SPI_CRC_ERR bit (Bit

1) in STATUS0 is set, and the command is not processed. This

behavior can be disabled by the CRC_EN_SPI_WRITE bit (Bit 1) in

the CONFIG0 register.

CRC of Response Packet

Each response from the ADE9103/ADE9112/ADE9113 is protected

by a CCITT-16 CRC with a polynomial of x16 + x12 + x5 + 1, with an

initial value of 0xffff, also known as CCITT-False, which ensures a

nonzero output with zero input.

SYNCHRONIZING MULTIPLE ADE9103/

ADE9112/ADE9113 DEVICES

There are two methods for clocking multiple ADE9103/ADE9112/

ADE9113 which are described in the Power-Up and Initialization

Procedures section. By initializing multiple ADE9103/ADE9112/

ADE9113 as described, all devices are using the same clock

frequency. To configure all ADE9103/ADE9112/ADE9113 devices

in an energy meter and provide coherent ADC output samples

obtained in the same output cycle, all ADE9103/ADE9112/ADE9113

devices must have the same ADC output frequency in addition to

a shared clock frequency. The DATAPATH_CONFIG bits (Bits[2:0])

in the CONFIG_FILT register selects the ADC output frequency;

therefore, they must be initialized to the same value (see the ADC

Output Values section for more details).

To ensure the ADC outputs of all ADE9103/ADE9112/ADE9113

devices generate samples synchronously, the MCU can perform an

ALIGN, which can be used in either dedicated SPI or daisy chain.

Setting the PREP_BROADCAST = 1 sets the ADE9103/ADE9112/

ADE9113 MISO pin to a high impedance state for the duration of

the next SPI frame. For devices configured with dedicated SPI,

set PREP_BROADCAST = 1 in the SYNC_SNAP register to pre-

vent contention between multiple device outputs sharing the same

signal. For devices configured in daisy-chain SPI, PREP_BROAD-

CAST = 0 in the SYNC_SNAP register.

The ADE9103/ADE9112/ADE9113 contains an internal 14-bit coun-

ter that functions at the XTALIN frequency. The counter is synchron-

ized with the ADC output period and the CLKOUT/DREADY pin.

When a new output period starts, the counter starts decreasing

from a value determined by the DATAPATH_CONFIG bits in the

CONFIG_FILT register. Table 17 details these values. Monitoring

this counter enables the user to observe if any ADE9103/ADE9112/

ADE9113 device is out of sync.

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