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Data Sheet

ADE9103/ADE9112/ADE9113

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. A | 14 of 55

Figure 8. ADE9103 Pin Configuration

Table 11. ADE9103 Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3

No Connect. Pin 1 and Pin 3 are connected together internally. These NC pins have no internal connection.

NIC

Not Connected Internally. The NIC pin has no internal connection.

4, 24

VDD

Primary Supply Voltage. The VDD pins provide the supply voltage for the ADE9103. Maintain the supply voltage at 3.3 V ±

10% for the specified operation. Decouple the VDD pins to the closest DGND pin with a 4.7 µF capacitor in parallel with a

ceramic 100 nF capacitor.

5, 11, 18, 25

DGND

Ground Reference.

ALDOOUT

1.8 V Output of Analog LDO Regulator. Decouple the ALDOOUT pin with a 4.7 µF capacitor in parallel with a ceramic 100

nF capacitor to DGND, Pin 5. Do not connect the external load circuitry to the ALDOOUT pin.

V2P

Positive Analog Input for the V2 Voltage Channel. V2P and V2M are differential voltage inputs with a maximum single-ended

signal level of ±500 mV with respect to the VxM pins for specified operation. Use the V2P and V1P pins with the related

input circuitry, as shown in Figure 27. If the V2 voltage channel is not used, connect the V2P pin to the V2M pin.

V2M

Negative Analog Input for the V2 Voltage Channel.

V1P

Positive Analog Inputs for the V1 Voltage Channel. The voltage channels are used with the voltage transducers. V1P and

V1M are differential voltage inputs with a maximum single-ended signal level of ±500 mV with respect to the VxM pins for

specified operation. Use the V1P and V2P pins with the related input circuitry, as shown in Figure 27. If the V1 voltage

channel is not used, connect the V1P pin to the V1M pin.

V1M

Negative Analog Input for the V1 Voltage Channel.

REFOUT

Voltage Reference Output. The REFOUT pin provides access to the on-chip voltage reference. The on-chip reference has a

nominal value of 1.25 V. Decouple the REFOUT pin to DGND, Pin 11, with a 4.7 µF capacitor in parallel with a ceramic 100

nF capacitor. Do not connect external load circuitry to the REFOUT pin.

Negative Analog Input for the Current Channel. The current channel is used with shunts. IM and IP are pseudo differential

voltage inputs with a maximum differential level of ±31.25 mV. Use the IM and IP pins with the related input circuitry, as

shown in Figure 27.

Positive Analog Input for the Current Channel.

IRQ

Interrupt Request Output. The IRQ pin is an active low logic open drain outputwith weak internal pull-up resistor.

Zero-Crossing Output Pin. The ZX pin must float when unused.

CLKOUT/DREADY

Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple ADE9103/ADE9112/

ADE9113 Devices section for details), the ADE9103 generates a digital signal synchronous to the main clock at the XTALIN

pin. Use CLKOUT to provide a clock to other ADE9103/ADE9112/ADE9113 devices. Data Ready, Active Low (DREADY).

When DREADY functionality is selected (see the Synchronizing Multiple ADE9103/ADE9112/ADE9113 Devices section for

details), the ADE9103 generates an active low signal synchronous to the ADC output frequency. Use this signal to start

reading the ADC outputs of the ADE9103.

MOSI

Data Input for the SPI Port.

MISO

Data Output for the SPI Port. Attach a 10 kΩ pull-up resistor to the VDD supply voltage for increased electromagnetic

compatibility (EMC) robustness.

SCLK

Serial Clock Input for the SPI Port. All serial data transfers are synchronized to this clock (see Table 3 for SPI interface

timing parameters and SPI Compatible Communication section for additional SPI port details).

Chip Select for the SPI Port (Active Low).

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