ADE9112 datasheet(27/55 Pages) AD

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Data Sheet

ADE9103/ADE9112/ADE9113

THEORY OF OPERATION

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Rev. A | 27 of 55

PROTECTING THE INTEGRITY OF

CONFIGURATION REGISTERS

The configuration lock feature protects the ADE9103/ADE9112/

ADE9113 configuration registers from unwanted changes. To ena-

ble this feature, write the Lock Key 0xD4 to the WR_LOCK register

(Address 0x01F). To disable this feature, write the Unlock Key

0x5E.

To determine whether the feature is enabled or disabled read back

the WR_LOCK register. This register reads back as the lock or

unlock key corresponding to the state it is in.

When this feature is enabled, it prevents writing from Address

0x001 to Address 0x018.

CRC OF CONFIGURATION REGISTERS

A 16-bit CRC is calculated over the configuration registers approx-

imately every 8 ms. The result is stored in CRC_RESULT bits,

which is split into a high and low byte, CRC_RESULT_HI and

CRC_RESULT_LO. The default value in the CRC_RESULT bits is

the CRC result of the default configuration registers. If there is a

change in the CRC result, the CRC_CHG bit inside of STATUS0

is set. The configuration registers, CONFIG0, CONFIG_FILT, CON-

FIG_ISO_ACC, EMI_CONFIG, EMI_HI_MASK, EMI_LO_MASK,

MASK0, MASK1, MASK2, CONFIG_ZX, SCRATCH, as well as

other critical reserved registers are covered by this CRC. The CRC

calculation cannot be disabled.

The CRC calculation of the configuration registers can also be

performed on command by writing to the CRC_FORCE bit in the

CONFIG_CRC register. Writing the CRC_FORCE bit resets the

CRC interval counter and deasset CRC_DONE if previously set

until the CRC calculation is complete. The CRC_FORCE bit is

cleared and the CRC_DONE bit is set once the CRC calculation is

complete. If CRC_FORCE is written high and then rewritten high or

low while recalculating, the second write is ignored. See Table 20

for more details.

STATUS REGISTERS

The bits in the STATUS0, STATUS1, and STATUS2 registers of the

ADE9103/ADE9112/ADE9113 characterize the state of the device.

At power-up, or after a hardware or software reset, the ADE9103/

ADE9112/ADE9113 signal the end of the reset period by setting

Bit 5 (RESET_DONE) to 1 in the STATUS0 register, indicating that

the IC is ready for SPI transactions. Then, Bit 4 (COM_UP) of

STATUS0 gets set to 1 to indicate that the entire IC is up and ready

to transmit the ADC waveform data.

The COMFLT_ERR bit (Bit 0) in the STATUS0 register indicates

when there was a communications failure across the isolation barri-

er. This status bit is used together with the COM_FLT_TYPE and

COM_FLT_COUNT registers. COM_FLT_TYPE gives more detail

as to the type of error that was detected across the isolation barrier,

and then, COM_FLT_COUNT keeps track of the number of error

correction codes (ECC) or physical layer (PHY) errors from the ISO

side to the NONISO side. ECC across the isolation barrier allows

1-bit detect and 1-bit correct and increases the communication

robustness across the barrier. Even though the ADE9103 does not

have isolation, the ECC function of the internal communication is

still present.

The STATUS0 and STATUS1 registers can be read by executing an

SPI register read. STATUS0 and STATUS1 can also be read as part

of the long SPI read operation. See the SPI Long Format Operation

and the SPI Short Format Operation sections for more information.

The STATUS2 register provides insight into internal errors that have

been detected and corrected. No additional actions are required

outside of acknowledging the change through a write 1 command. If

a bit in STATUS2 is continuously being set, this could indicate that

the ADE9103/ADE9112/ADE9113 is in an unrecoverable state.

For more information on individual bits in the STATUSx registers, go

to the bit field descriptions in the Table 20 section.

ZERO CROSSING

The ADE9103/ADE9112/ADE9113 devices have independent zero

crossing detection circuits on each ADC channel. The ZX pin

indicates a zero crossing event and can be used to extract a low

latency power line frequency measurement. Other common uses

for zero crossing detection are indicating opportunities to open and

close relay contacts for minimal switching voltage or deriving time

periods when power line voltage is sufficiently low for power-line

communications in energy metering and programmable logic con-

troller (PLC) systems. See zero crossing output latency and jitter

specification in Table 2.

The ZX_CHANNEL_CONFIG bits in the CONFIG_ZX register set

which ADC channel zero crossing detection circuit is routed to the

ZX output pin. The response and behavior of the ZX pin output are

selectable and allow the flexibility to choose which zero crossing

events are reported by setting the ZX_EDGE_SEL bits. Options

and settings for the CONFIG_ZX register are described in Table 20.

The ZX pin output is disabled by default.

The input of each zero crossing detection circuit has a first order

LPF to filter line harmonics. The typical cutoff frequency is 80 Hz.

The V1 and V2 voltage channels both have integrated hysteresis to

minimize the effects of line noise and bounce. The current channel

does not have hysteresis.

INTERRUPTS

The ADE9103/ADE9112/ADE9113 have two methods for indicating

an event has occurred: the STATUS0, STATUS1, and STATUS2

registers and the IRQ pin. Details for the STATUS0, STATUS1, and

STATUS2 registers can be found in Status Registers and Table

20. The interrupt pin (IRQ), connected to the STATUSx registers

through the MASKx registers, helps detect critical faults to create

a reliable and robust system. The IRQ pin is open drain, allowing

multiple interrupts to be connected together with a single 10 kΩ

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