CDCS503-Q1

SCAS924B – MARCH 2012 – REVISED JUNE 2012

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DESCRIPTION

The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency

multiplication.

It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage

of the CDCS502, and the CDCS503-Q1 has an output enable pin.

The device accepts a 3.3-V LVCMOS signal at the input.

The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input

frequency or multiplied by the factor of four.

The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock

frequency with a triangular modulation.

By this, the device can generate output frequencies between 8 MHz and 108 MHz with or without SSC.

A separate control pin can be used to enable or disable the output. The CDCS503-Q1 device operates in a 3.3-V

environment.

It is characterized for operation from –40°C to 105°C, and available in an 8-pin TSSOP package.

Table 1. FUNCTION TABLE

OE

FS

SSC_SEL 0

SSC_SEL 1

SSC AMOUNT

fOUT/fIN

fOUT at fin = 27 MHz

0

x

x

x

x

x

3-state

1

0

0

0

±0.00%

1

27 MHz

1

0

0

1

±0.50%

1

27 MHz

1

0

1

0

±1.00%

1

27 MHz

1

0

1

1

±2.00%

1

27 MHz

1

1

0

0

±0.00%

4

108 MHz

1

1

0

1

±0.50%

4

108 MHz

1

1

1

0

±1.00%

4

108 MHz

1

1

1

1

±2.00%

4

108 MHz

2

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