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WM8994ECS/R 数据表(PDF) 58 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 58 Page - Cirrus Logic

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WM8994
58
Rev 4.6
DMICCLK pin
DMICDATn pin
(Left & Right
channels interleaved)
1
2
1
2
1
2
Left Mic output
1
1
1
Right Mic output
2
2
2
hi-Z
Figure 20 Digital Microphone Interface Timing
The four digital microphone channels can be routed to one of the four timeslots on AIF1. The
DMICDAT1 microphones, when enabled, are routed to the Left/Right channels of AIF1 Timeslot 0.
The DMICDAT2 microphones, when enabled, are routed to the Left/Right channels of AIF1 Timeslot
1.
Digital volume control of the digital microphone channels in the AIF1 signal paths is provided using
the registers described in the “Digital Volume and Filter Control” section.
The digital microphone channels can be routed, in a limited number of configurations, to the digital
mixing output bus, via the digital sidetone signal paths. See “Digital Mixing” for further details.
Digital volume control of the digital microphone channels in the digital sidetone signal paths is
provided using the registers described in the “Digital Mixing” section.
The digital microphone interface control fields are described in Table 9.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4 (0004h)
Power
Managemen
t (4)
5
DMIC2L_ENA
0
Digital microphone DMICDAT2
Left channel enable
0 = Disabled
1 = Enabled
4
DMIC2R_ENA
0
Digital microphone DMICDAT2
Right channel enable
0 = Disabled
1 = Enabled
3
DMIC1L_ENA
0
Digital microphone DMICDAT1
Left channel enable
0 = Disabled
1 = Enabled
2
DMIC1R_ENA
0
Digital microphone DMICDAT1
Right channel enable
0 = Disabled
1 = Enabled
Table 9 Digital Microphone Interface Control



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