WM8994ECSSLASHR datasheet(32/363 Pages) CIRRUS

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WM8994

Rev 4.6

TYPICAL SIGNAL LATENCY

OPERATING MODE

TEST CONDITIONS

LATENCY

AIF1

AIF2

DIGITAL CORE

AIF2 to DAC Stereo Path

AIF2 EQ enabled,

AIF2 3D enabled,

AIF2 DRC enabled,

SRC enabled

fs=8kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 1536fs

SYSCLK=AIF1CLK

1.4ms

fs=48kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 1536fs

SYSCLK=AIF1CLK

1.3ms

fs=8kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 256fs

SYSCLK=AIF1CLK

1.7ms

fs=48kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 256fs

SYSCLK=AIF1CLK

1.4ms

ADC to AIF2 Stereo Path

Digital Sidetone HPF enabled,

AIF2 DRC enabled,

AIF2 HPF enabled,

SRC enabled

fs=8kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 256fs

SYSCLK=AIF1CLK

2.2ms

fs=48kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 256fs

SYSCLK=AIF1CLK

1.2ms

Digital Sidetone HPF disabled,

AIF2 DRC disabled,

AIF2 HPF disabled,

SRC disabled

fs=8kHz,

Clock rate = 1536fs

SYSCLK=AIF2CLK

1.3ms

Digital Sidetone HPF disabled,

AIF2 DRC disabled,

AIF2 HPF disabled,

SRC enabled

fs=48kHz,

Clock rate = 256fs

fs=8kHz,

Clock rate = 1536fs

SYSCLK=AIF1CLK

1.1ms

Notes:

1. These figures are relevant to typical voice call modes, assuming AIF2 is connected to the baseband processor

2. The SRC (Sample Rate Converter) is enabled automatically whenever required

WM8994ECS/R 数据表(PDF) 32 Page - Cirrus Logic

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WM8994ECS/R 数据表(PDF) 32 Page - Cirrus Logic

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