WM8994ECSSLASHR datasheet(71/363 Pages) CIRRUS

71 / 363 page

WM8994

Rev 4.6

“Digital Audio Interface Control”. See “General Purpose Input/Output” to configure the GPIO1 pin as

ADCLRCLK1. The ADCLRCLK1

rate is controlled as described in “Digital Audio Interface Control”.

When

ultrasonic mode is enabled, the audio band filtering and digital volume controls (see “Digital

Volume and Filter Control

”) are bypassed on the affected output paths.

The Dynamic Range Control (DRC) function is not available on the AIF1 output signal paths in

ultrasonic mode. Note, however, that the DRC is still available on the AIF input paths in this case.

The ultrasonic (4FS) signal paths are illustrated in Figure 23. The AIF1ADC_4FS register bit is defined

in Table 21.

AIF1ADC_4FS

DIGITAL AUDIO

INTERFACE 1 (AIF1)

Left / Right source select / Mono Mix control

AIF1 Slot 1

AIF1 Slot 0

AIF1 Slot 1

AIF1 Slot 0

fs / 4fs Select

DRC

Figure 23 Ultrasonic (4FS) Signal Paths

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1040 (0410h)

AIF1 ADC1

Filters

AIF1ADC_4FS

Enable AIF1ADC ultrasonic mode

(4FS) output, bypassing all AIF1

baseband output filtering

0 = Disabled

1 = Enabled

Table 21 Ultrasonic (4FS) Mode Control

WM8994ECS/R 数据表(PDF) 71 Page - Cirrus Logic

WM8994ECS/R 数据表(HTML) 71 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载