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WM8994ECS/R 数据表(PDF) 36 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 36 Page - Cirrus Logic |
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36 / 363 page  WM8994 36 Rev 4.6 DIGITAL AUDIO INTERFACE - MASTER MODE BCLK (output) LRCLK (output) ADCDAT (output) DACDAT (input) tDDA tDHT tDST tDL tBCY VOH VOL VOH VOL VOH VOL VIH VIL Figure 4 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 4 shows the default, non- inverted polarity of these signals. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode BCLK cycle time tBCY 160 ns LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 48 ns DACDAT setup time to BCLK rising edge tDST 32 ns DACDAT hold time from BCLK rising edge tDHT 10 ns Audio Interface Timing - Ultrasonic (4FS) Master Mode BCLK cycle time tBCY 80 ns ADCDAT propagation delay from BCLK falling edge tDDA 24 ns Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. |
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