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WM8994ECS/R 数据表(PDF) 272 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 272 Page - Cirrus Logic |
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272 / 363 page  WM8994 272 Rev 4.6 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R48 (30h) Output Mixer (4) 11:9 IN2RP_MIXOUT R_VOL [2:0] 000 IN2RP to MIXOUTR Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 8:6 IN2RN_MIXOUT R_VOL [2:0] 000 IN2RN to MIXOUTR Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 5:3 IN1L_MIXOUTR _VOL [2:0] 000 IN1L PGA Output to MIXOUTR Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 2:0 IN1R_MIXOUTR _VOL [2:0] 000 IN1R PGA Output to MIXOUTR Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB Register 30h Output Mixer (4) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R49 (31h) Output Mixer (5) 11:9 DAC1L_MIXOU TL_VOL [2:0] 000 Left DAC1 to MIXOUTL Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 8:6 IN2RN_MIXOUT L_VOL [2:0] 000 IN2RN to MIXOUTL Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 5:3 MIXINR_MIXOU TL_VOL [2:0] 000 MIXINR Output (Right ADC bypass) to MIXOUTL Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB 2:0 MIXINL_MIXOU TL_VOL [2:0] 000 MIXINL Output (Left ADC bypass) to MIXOUTL Volume 0dB to -21dB in 3dB steps 000 = 0dB 001 = -3dB …(3dB steps) 111 = -21dB Register 31h Output Mixer (5) |
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