TDA7546 datasheet(32/68 Pages) STMICROELECTRONICS

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Functional description

TDA7546

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error corrections done on good quality marked RDS bits. Then the RDS module is

synchronized. This is indicated by “synch” bit rds_int[4] which is set if the flywheel counter is

greater than zero. Every valid consecutive RDS block (A, B, C or C’, D, A, B...) increments

the flywheel counter by two.

If the next consecutive RDS block has its syndrome not zero, or corrections are done on

good quality marked RDS bits, then the flywheel counter decrements by one. If the flywheel

counter becomes zero, then a new RDS block synchronization will be performed. If blocks of

type E are detected (indicated by “e” bit rds_qu[1]), then the flywheel counter will be not

modified, because in case of European RDS, block E is an error but not in case of USA

BRDS. This means E blocks are treated as neutral in this RDS/BRDS implementation.

The “data_ok” bit rds_corrp[1] is set only, if the flywheel counter is greater than two, the

syndrome of the detected RDS block is zero and if no error corrections are done on good

quality marked RDS bits.

Figure 7 shows an example for the flywheel mechanism.

The first diagram shows the relative signal quality of 26 received RDS bits. 100% means

that the last received 26 RDS bits are all marked as good by the demodulator and 0% that

all are marked as bad.

The second diagram gives information about the flywheel counter status. The counter value

could be between 0 and 63.

The next two charts showing the bits “synch” rds_int[4] and “data_ok” rds_corrp[1]

The last graph indicates every generated buffer not empty (bne) interrupt. After each

interrupt the RDS data will be read out from the RAM buffer (within 22 ms), before next RDS

block is written into. This is done to reset the interrupt flag “int” rds_int[0] each time. Further

the “syncw” bit rds_bd_ctrl[0] is set to one, to store only synchronized RDS blocks .

The following case is considered now: First the receiving condition is good (section 1), then

it is going to be worse (section 2) because of entering a tunnel, after leaving it is going to be

better again (section 3).

Section 1:

After power up or resynchronization (“ar_res”, rds_int[5]), the first recognized RDS

block is stored in the RAM buffer and generates an “bne” interrupt. At the same

time “synch” bit rds_int[4] is set to one. With the next stored RDS block the

“data_ok” bit rds_corrp[1] is set, because the flywheel counter becomes greater

than two.

With every next RDS block the flywheel counter increments by two, until the upper

margin of 63 is reached.

Section 2:

Because of entering a tunnel, the demodulator increases bad marked RDS bits

until all are marked as bad. The flywheel counter decrements by one after each

new RDS block because of error corrections done on good marked RDS bits or

because the syndrome of the expected block was not zero after error correction.

The “data_ok” bit rds_corrp[1] is set to zero whenever the flywheel counter

decrements. Note that the synchronization flag “synch” rds_int[4] is set and the

interrupt is performed after every expected RDS block, until the flywheel counter is

zero.

Then the RDS is desynchronized. Now spurious interrupts could occur because of

random RDS blocks detected during resynchronization process. If the time of

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