CC1070-RTR1 datasheet(29/57 Pages) TI2

29 / 57 page

CC1070

SWRS043A

Page 29 of 54

14 Frequency Synthesizer

14.1 VCO, Charge Pump and PLL Loop Filter

The VCO is completely integrated and

operates in the 1608 – 1880 MHz range. A

frequency divider is used to get a

frequency in the UHF range (402 – 470

and 804 – 940 MHz). The BANDSELECT

bit in the ANALOG register selects the

frequency band.

The VCO frequency is given by:

⎟

⎠

⎞

⎜

⎝

⎛

⋅

8192

DITHER

FREQ

ref

VCO

The VCO frequency is divided by 2 and by

4 to generate frequencies in the two

bands, respectively.

The VCO sensitivity (sometimes referred

to as VCO gain) varies over frequency and

operating conditions. Typically the VCO

sensitivity varies between 12 and 36

MHz/V. For calculations the geometrical

mean at 21 MHz/V can be used. The PLL

calibration (explained below) measures

the actual VCO sensitivity and adjusts the

charge pump current accordingly to

achieve correct PLL loop gain and

bandwidth (higher charge pump current

when VCO sensitivity is lower).

The following equations can be used for

calculating PLL loop filter component

values, see Figure 3, for a desired PLL

loop bandwidth, BW:

C7 = 3037 (fref / BW

2) –7

[pF]

R2 = 7126 (BW / fref)

[kΩ]

C6 = 80.75 (fref / BW

[nF]

R3 = 21823 (BW / fref)

[kΩ]

C8 = 839 (fref / BW

2) –6

[pF]

Define a minimum PLL loop bandwidth as

BWmin =

220

ref

⋅

. If BWmin >

Baud rate/3 then set BW = BWmin and if

BWmin < Baud rate/3 then set BW = Baud

rate/3 in the above equations.

There are two special cases when using

the recommended 14.7456 MHz crystal:

1) If the data rate is 4.8 kBaud or below

and the RF operating frequency is in the

402 – 470 MHz frequency range the

following loop filter components are

recommended:

C6 = 220 nF

C7 = 8200 pF

C8 = 2200 pF

R2 = 1.5 kΩ

R3 = 4.7 kΩ

2) If the data rate is 4.8 kBaud or below

and the RF operating frequency is in the

804 – 940 MHz frequency range the

following loop filter components are

recommended:

C6 = 100 nF

C7 = 3900 pF

C8 = 1000 pF

R2 = 2.2 kΩ

R3 = 6.8 kΩ

After calibration the PLL bandwidth is set

by the PLL_BW register in combination

with the external loop filter components

calculated above. The PLL_BW can be

found from

PLL_BW = 146 + 16 log2(fref /7.126)

where fref is the reference frequency (in

MHz). The PLL loop filter bandwidth

increases with increasing PLL_BW setting.

After calibration the applied charge pump

current (CHP_CURRENT[3:0]) can be

read in the STATUS1 register. The charge

pump current is approximately given by:

[]

CURRENT

CHP

⋅

The combined charge pump and phase

detector gain (in A/rad) is given by the

charge pump current divided by 2

π.

The PLL bandwidth will limit the maximum

modulation frequency and hence data

rate.

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