CC1070-RTR1 datasheet(9/57 Pages) TI2

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CC1070

SWRS043A

Page 9 of 54

4.3 Frequency Synthesizer Section

Parameter

Min.

Typ.

Max.

Unit

Condition / Note

Phase noise, 402 – 470 MHz

12.5 kHz channel spacing

−87

−95

−100

−105

−114

dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 10.

The phase noise will be higher for

larger PLL loop filter bandwidth.

Phase noise, 804 - 940 MHz

25 kHz channel spacing

−81

−89

−96

−103

−122

dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 10.

The phase noise will be higher for

larger PLL loop filter bandwidth.

PLL loop bandwidth

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

kHz

After PLL and VCO calibration.

The PLL loop bandwidth is

programmable

PLL lock time (TX_1 / TX_2 turn

time)

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

500 kHz channel spacing

180

270

One channel frequency step to

RF frequency within ±10% of

channel spacing. Depends on

loop filter component values and

PLL_BW register setting. See

Table 20 on page 32 for more

details.

PLL turn-on time. From power

down mode with crystal oscillator

running.

12.5 kHz channel spacing, 433 MHz

25 kHz channel spacing, 868 MHz

500 kHz channel spacing

3.2

2.5

700

Time from writing to registers to

RF frequency within ±10% of

channel spacing. Depends on

loop filter component values and

PLL_BW register setting. See

Table 19 on page 32 for more

details.

Table 5. Frequency synthesizer parameters

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