LP8553

SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

www.ti.com

PWM_RES[1:0]

00

01

10

11

PWM_FREQ[4:0]

5 MHz

10 MHz

20 MHz

40 MHz

Resolution (bits)

01101

3155

6311

12621

-

10

01100

3005

6010

12020

-

10

01011

2855

5710

11419

-

10

01010

2705

5409

10818

-

10

01001

2554

5109

10217

-

10

01000

2404

4808

9616

19232

11

00111

2179

4357

8715

17429

11

00110

1953

3907

7813

15626

11

00101

1728

3456

6912

13823

11

00100

1503

3005

6010

12020

11

00011

1202

2404

4808

9616

12

00010

1052

2104

4207

8414

12

00001

826

1653

3306

6611

12

00000

601

1202

2404

4808

13

RFSET resistance values with corresponding PWM frequencies:

PWM_RES[1

00

01

10

11

:0]

RFSET (k

Ω)

5 MHz Clock

Resolution

10 MHz

Resolution

20 MHz

Resolution

40 MHz

Resolution

Clock

Clock

Clock

10...15

19232

8

19232

9

19232

10

19232

11

26...29

16828

8

15927

9

16227

10

17429

11

36...41

14424

8

12771

9

14424

10

15626

11

50...60

12020

8

9616

10

12020

10

12020

11

85...100

9616

9

8715

10

9616

11

9616

12

135...150

7963

9

7813

10

7813

11

8414

12

200...300

6386

9

6311

10

6010

11

6811

12

450...

4808

10

4808

11

4808

12

4808

13

Phase Shift PWM Scheme

Phase shift PWM scheme allows delaying the time when each LED output is active. When the LED output are

not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the

ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output

ceramic capacitor audible ringing. PSPWM scheme also increases the load frequency seen on boost output by

x4 and therefore transfers the possible audible noise to so high frequency that human ear cannot hear it.

Description of the PSPWM mode is seen on the following diagram. PSPWM mode is enabled by setting

<EN_PSPWM> EEPROM bit to 1. Shift time is the delay between outputs and it is defined as 1 / (fPWM x 4). If the

<EN_PSPWM> bit is 0, then the delay is 0 and all outputs are active simultaneously.

16

Submit Documentation Feedback

Copyright © 2011–2014, Texas Instruments Incorporated

Product Folder Links: LP8553