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LP8553 数据表(PDF) 8 Page - Texas Instruments |
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LP8553 数据表(HTML) 8 Page - Texas Instruments |
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8 / 41 page ![]() LP8553 SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014 www.ti.com Logic Interface Characteristics (continued) Symbol Parameter Condition Min Typ Max Units Logic Input PWM VIL Input Low Level 0.2xVDDIO V VIH Input High Level 0.8xVDDIO V II Input Current −1.0 1.0 μA Logic Inputs SCL, SDA VIL Input Low Level 0.2xVDDIO V VIH Input High Level 0.8xVDDIO V II Input Current −1.0 1.0 μA Logic Outputs SDA, FAULT VOL Output Low Level IOUT = 3 mA (pull-up current) 0.3 0.5 V IL Output Leakage Current VOUT = 2.8V −1.0 1.0 μA I 2C Serial Bus Timing Parameters (SDA, SCLK) (1) Limit Symbol Parameter Units Min Max fSCLK Clock Frequency 400 kHz 1 Hold Time (repeated) START Condition 0.6 μs 2 Clock Low Time 1.3 μs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START 1.3 μs Condition Capacitive Load Parameter for Each Bus Line Cb 10 200 ns Load of 1 pF corresponds to 1 ns. (1) Ensured by design. VDDIO = 1.65V to 5.5V. 8 Submit Documentation Feedback Copyright © 2011–2014, Texas Instruments Incorporated Product Folder Links: LP8553 |
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