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STA326

5

FUNCTIONAL DESCRIPTION

5.1 PIN DESCRIPTION

5.1.1

OUT1A, 1B, 2A & 2B (Pins 16, 10, 9 & 3)

Output Half Bridge PWM Outputs 1A, 1B, 2A & 2B provide the inputs signals to the speaker devices.

Half Bridge Power Outputs 1A, 1B, 2A & 2B deliver audio power to the speaker loads. Using DDX stereo

configuration mode, outputs 1A (+) and 1B (-) comprise Channel 1 and outputs 2A (+) and 2B (-) comprise

Channel 2. Using binary 2.1 channel configuration mode, output 1A is for Channel 1 and output 1B is for

Channel 2 and outputs 2A (+) and 2B (-) comprise Channel 3. Using DDX mono-high power output mode

(Config connected to VREG1), outputs 1A and 1B are shorted (+) and outputs 2A and 2B are shorted (-)

comprising a single BTL output with twice output current capability for Channel 3.

5.1.2

RESET (Pin 22)

Driving RESET low sets all outputs low and returns all register settings to their defaults. The reset is asyn-

chronous to the internal clock.

5.1.3

The SDA (I2C Data) and SCL (I2C Clock) pins operate per the I2C specification. See Section 4.0. Fast-

mode (400kB/sec) I2C communication is supported.

5.1.4

GNDA & VDDA: Phase Locked Loop Power (Pins 28-29)

The phase locked loop power is applied here. This +3.3V supply must be well bypassed and filtered for

noise immunity. The audio performance of the device is critically dependent upon the PLL circuit.

5.1.5

CLK: Master Clock In (Pin 27)

This is the master clock in required for the operation of the digital core. The master clock must be an in-

teger multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256*Fs) for

a 48kHz sample rate, which is the default at power-up. Care must be taken to avoid over-clocking the

device i.e provide the device with the nominally required system clock; otherwise, the device may not prop-

erly operate or be able to communicate.

5.1.6

FILTER_PLL: PLL Filter (Pin 26)

PLL Filter connects to external filter components for PLL loop compensation. Refer to the schematic dia-

gram for the recommended circuit.

5.1.7

BICKI: Bit Clock In (Pin 32)

The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*Fs, for ex-

ample using I2S serial format.

5.1.8

SDI_12: Serial Data Input (Pin 30)

PCM audio information enters the device here. Six format choices are available including I2S, left- or right-

justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

5.1.9

CONFIG: Configuration input (Pin 21)

The configuration input pin is normally connected to ground. Using the mono-high power BTL configura-

tion requires the CONFIG input pin be shorted to VREG1.

5.1.10 LRCKI: Left/Right Clock In (Pin 31)

The Left/Right clock input is for data word framing. The clock frequency will be at the input sample rate Fs.

5.2 AUDIO PERFORMANCE

TBD