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STA326

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Table 12. DDX® Output Modes

7.4.2

DDX® Variable Compensating Pulse Size

The DDX® variable compensating pulse size is intended to adapt to different power stage ICs. Contact

Apogee applications for support when deciding this function.

7.4.3

DDX® Variable Compensating Pulse Size

The DDX® variable compensating pulse size is not recommended to be used except in special circum-

stances . Contact STMicroelectronics applications for support when deciding this function.

Table 13. DDX® Compensating Pulse

7.5 Configuration Register D (Address 03h)

7.5.1

High-Pass Filter Bypass

The STA326 features an internal digital high-pass filter for the purpose of DC Blocking. The purpose of

this filter is to prevent DC signals from passing through a DDX® amplifier. DC signals can cause speaker

damage.

OM (1,0)

Output Stage – Mode

Not Used

STA500/505/508

Variable Compensation

BIT

R/W

RST

NAME

DESCRIPTION

6...2

R/W

10000

CSZ (4...0)

Compensating Pulse Size Select

CSZ (4…0)

Compensating Pulse Size

00000

0 Clock period Compensating Pulse Size

00001

1 Clock period Compensating Pulse Size

……

10000

16 Clock period Compensating Pulse Size

……

11111

31 Clock period Compensating Pulse Size

MME

ZDE

DRC

BQL

PSL

DSPB

DEMP

HPB

BIT

R/W

RST

NAME

DESCRIPTION

R/W

HPB

High-Pass Filter Bypass Bit.

0 – AC Coupling High Pass Filter Enabled

1 – AC Coupling High Pass Filter Disabled

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