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7.7.1

Output Configuration Selection

Table 15. Output Configuration Selections

7.7.2

Invalid Input Detect Mute Enable

cally mute all outputs if the signals are perceived as invalid.

7.7.3

Binary Clock Loss Detection Enable

Detects loss of input MCLK in binary mode and will output 50% duty cycle to prevent audible artifacts when

input clocking is lost.

7.7.4

Auto-EAPD on Clock Loss Enable

When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection.

7.7.5

Powerdown

If the powerdown bit is set low, a powerdown sequence is initiated resulting in a soft mute of all the chan-

nels and PWM outputs are damped.

BIT

R/W

RST

NAME

DESCRIPTION

1…0

R/W

00

OCFG

(1…0)

Output Configuration Selection

00 – 2-channel (Full-bridge) Power, 1-channel DDX is default

OCFG (1...0)

Output Power Configuration

00

2 Channel (Full-Bridge) Power, 1 Channel DDX:

1A/1B

◊ 1A/1B

2A/2B

◊ 2A/2B

01

2(Half-Bridge).1(Full-Bridge) On-Board Power:

1A

◊ 1A

Binary

2A

◊ 1B

Binary

3A/3B

◊ 2A/2B Binary

10

Reserved

11

1 Channel Mono-Parallel:

3A

◊ 1A/1B

3B

◊ 2A/2B

BIT

R/W

RST

NAME

DESCRIPTION

2

R/W

1

IDE

Invalid Input Detect Auto-Mute Enable:

0 – Disabled

1 – Enabled

BIT

R/W

RST

NAME

DESCRIPTION

5

R/W

1

BCLE

Binary Output Mode Clock Loss Detection Enable

0 – Disabled

1 – Enabled

BIT

R/W

RST

NAME

DESCRIPTION

7

R/W

0

ECLE

Auto EAPD on Clock Loss

0 – Disabled

1 – Enabled

BIT

R/W

RST

NAME

DESCRIPTION

6

R/W

1

PWDN

Software Power Down:

0 – Powerdown mode operation (auto soft-mute enabled)

1 – Normal Operation