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STA326

7.1 CONFIGURATION REGISTER A (Address 00h)

7.1.1

Master Clock Select

The STA326 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, and 96kHz. Therefore the

internal clock will be:

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs).

The correlation between the input clock and the input sample rate is determined by the status of the MCSx

bits and the IR (Input Rate) register bits. The MCSx bits determine the PLL factor generating the internal

clock and the IR bit determines the oversampling ratio used internally.

Table 7. IR and MCS Settings for Input Sample Rate and Clock Rate

7.1.2

Interpolation Ratio Select

The STA326 has variable interpolation (re-sampling) settings such that internal processing and DDX out-

put rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-

through) or provides a down-sample by a factor of 2.

The IR bits determine the re-sampling ratio of this interpolation.

Table 8. IR bit settings as a function of Input Sample Rate

D7

D6

D5

D4

D3

D2

D1

D0

FDRB

TWAB

TFRB

IR1

IR0

MCS2

MCS1

MCS0

01100011

BIT

R/W

RST

NAME

DESCRIPTION

0

R/W

1

MCS0

Master Clock Select: Selects the ratio between the input

1R/W

1

MCS1

2R/W

0

MCS2

Input Sample Rate

fs (kHz)

IR

MCS(2..0)

000

001

010

011

100

101

32, 44.1, 48

00

768fs

512fs

384fs

256fs

128fs

576fs

88.2, 96

01

384fs

256fs

192fs

128fs

64fs

x

176.4, 192

1X

384fs

256fs

192fs

128fs

64fs

x

BIT

R/W

RST

NAME

DESCRIPTION

4...3

R/W

00

IR (1...0)

Interpolation Ratio Select: Selects internal interpolation ratio based

Input Sample Rate Fs (kHz)

IR (1,0)

32

00

2 times over-sampling

44.1

00

2 times over-sampling

48

00

2 times over-sampling

88.2

01

Pass-Through

96

01

Pass-Through

176.4

10

Down-sampling by 2

192

10

Down-sampling by 2