 2013-2016 Microchip Technology Inc.

Advance Information

DS40001735C-page 5

PIC18(L)F2X/4X/6XK40

FIGURE 3:

40-PIN PDIP PIN DIAGRAM FOR PIC18(L)F45K40, PIC18(L)F46K40,

PIC18(L)F47K40

FIGURE 4:

40-PIN UQFN (5x5x0.5 mm) PIN DIAGRAM FOR PIC18(L)F45K40, PIC18(L)F46K40,

PIC18(L)F47K40

2

3

4

5

6

7

8

9

10

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

RB6/ICSPCLK

RB5

RB4

RB0

VDD

VSS

RD2

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VDD

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD0

RD1

RC5

RC4

RD3

RD4

RC7

RC6

RD7

RD6

RD5

RB7/ICSPDAT

1

RB3

RB2

RB1

PIC18(L)F45K40

PIC18(L)F46K40

PIC18(L)F47K40

Note:

See Table 4 for location of all peripheral functions.

10

11

2

3

4

5

6

1

18 19 20

21

22

12 13 14 15

38

8

7

40 39

16 17

29

30

31

32

33

23

24

25

26

27

28

36

34

35

9

37

RC0

RA6

RA7

VSS

VDD

RE2

RE1

RE0

RA5

RA4

RC7

RD4

RD5

RD6

RD7

VSS

VDD

RB0

RB1

RB2

PIC18(L)F45K40

PIC18(L)F46K40

PIC18(L)F47K40

Note 1:

See Table 4 for location of all peripheral functions.

2:

It is recommended that the exposed bottom pad be connected to VSS.