RC1

29

—

—

—

—

—

RX4(1)

DT4(3)

—

T6IN(1)

—

—

—

—

IOCC1

SOSCI

RC2

33

—

—

—

—

—

—

—

—

—

—

CWG1IN(1)

—

IOCC2

—

RC3

34

—

—

—

—

SCL1(3,4)

SCK1(1)

—

—

—

—

—

—

—

IOCC3

—

RC4

35

—

—

—

—

SDA1(3,4)

SDI1(1)

—

—

—

—

—

—

—

IOCC4

—

RC5

36

—

—

—

—

—

—

—

—

—

—

—

—

IOCC5

—

RC6

31

—

—

—

—

—

CK1(3)

—

—

—

—

—

—

IOCC6

—

RC7

32

—

—

—

—

—

RX1(1)

DT1(3)

—

—

—

—

—

—

IOCC7

—

RD0

58

AND0

—

—

—

—

—

—

—

—

—

—

—

—

—

RD1

55

AND1

—

—

—

—

—

—

T5CKI(1)

T7G(1)

——

—

—

—

—

RD2

54

AND2

—

—

—

—

—

—

—

—

—

—

—

—

—

RD3

53

AND3

—

—

—

—

—

MDCARL(1)

——

—

—

—

—

—

RD4

52

AND4

—

—

—

—

—

MDCARH(1)

—

—

—

—

—

—

—

RD5

51

AND5

—

—

—

SDA2(3,4)

SDI2(1)

—

MDSRC(1)

——

—

—

—

—

—

RD6

50

AND6

—

—

—

SCL2(3,4)

SCK2(1)

—

—

—

—

—

—

—

—

—

RD7

49

AND7

—

—

—

SS2(1)

——

—

—

—

—

—

—

—

RE0

2

ANE0

—

—

—

—

CK3(3)

—

—

—

—

—

—

IOCE0

—

RE1

1

ANE1

—

—

—

—

RX3(1)

DT3(3)

——

—

—

—

—

IOCE1

—

RE2

64

ANE2

—

—

—

—

CK5(3)

—

—

—

—

—

—

IOCE2

—

RE3

63

ANE3

—

—

—

—

RX5(1)

DT5(3)

——

—

—

—

—

IOCE3

—

RE4

62

ANE4

—

—

—

—

—

—

T4IN(1)

—

CCP5(1)

—

—

IOCE4

—

RE5

61

ANE5

—

—

—

—

—

—

—

—

CCP4(1)

——

IOCE5

—

TABLE 5:

64-PIN ALLOCATION TABLE PIC18(L)F6XK40 (CONTINUED)

Note

1:

This is a PPS remappable signal. The input function may be removed from the default location shown to one of several other PORTx pins. Details about this can be found in the data sheet.

2:

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several POTRTx pin options. Details about this can be found in the data sheet.

3:

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

4:

These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels will be

standard TTL/ST as selected b the INLVL register, instead of the I2C specific input buffer thresholds.