SN260 datasheet(22/88 Pages) STMICROELECTRONICS

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SPI protocol

SN260

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SPI protocol

The SN260 low level protocol centers on the SPI interface for communication with a pair of

GPIO for handshake signaling.

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The SN260 looks like a hardware peripheral.

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The SN260 is the slave device and all transactions are initiated by the Host (the

master).

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The SN260 supports a reasonably high data rate.

6.1

Physical interface configuration

The SN260 supports both SPI Slave Mode 0 (clock is idle low, sample on rising edge) and

SPI Slave Mode 3 (clock is idle high, sample on rising edge) at a maximum SPI clock rate of

5MHz, as illustrated in Figure 3.

Note:

The convention for the waveforms in this document is to show Mode 0.

Figure 3.

SPI transfer format, Mode 0 and Mode 3

The nHOST_INT signal and the nWAKE signal are both active low. The Host must supply a

pull-up resistor on the nHOST_INT signal to prevent errant interruptions during undefined

events such as the SN260 resetting. The SN260 supplies an internal pull-up on the nWAKE

signal to prevent errant interruptions during undefined events such as the Host resetting.

6.2

SPI transaction

The basic SN260 SPI transaction is half-duplex to ensure proper framing and to give the

SN260 adequate response time. The basic transaction, as shown in Figure 4, is composed

of three sections: Command, Wait, and Response. The transaction can be considered

analogous to a function call. The Command section is the function call, and the Response

section is the return value.

Figure 4.

General timing diagram for a SPI transaction

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