SLAS366 datasheet(18/56 Pages) TI2

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3–6

In turbo mode see Section 3.8.3.

3.6.2

Serial Data Out (DOUT)

DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data word

is the ADC conversion result. In the control frame, the data is the register read results when requested by the

read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all zeroes. Valid

data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The first bit transmitted

on the falling edge of FS is the MSB of valid data.

3.6.3

Serial Data In (DIN)

The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of FS. In a data

frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the LSB (D0) is

set to 1 to switch from the continuous data transfer mode to the programming mode. In a control frame, the data is

the control and configuration data that sets the device for a particular function as described in Section 3.9, Control

3.6.4

Frame-Sync FS

The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin is

connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).

Data is valid on the falling edge of the FS signal.

The frequency of FS is defined as the sampling rate of the TLV320AIC15 and derived from the master clock MCLK

as followed (see Section 3.1 Operating Frequencies for details):

FS = MCLK / (16

× P × N × M)

SCLK

DIN/DOUT

(16 Bit)

MSB

LSB

D15

D14

D15

16 SCLKs

Figure 3–5. Timing Diagram of FS

3.6.5

Cascade Mode and Frame-Sync Delayed (FSD)

In cascade mode, the DSP receives all frame-sync pulses from the master though the master’s FS. The master’s FSD

is output to the first slave and the first slave’s FSD is output to the second slave device and so on. Figure 3–7 shows

the cascade of 4 TLV320AIC15s in which the closest one to DSP is the master and the rest are slaves. The FSD output

of each device is input to the FS terminal of the succeeding device. Figure 3–8 shows the FSD timing sequence in

the cascade.

3.6.6

Stand-Alone Slave

In the stand-alone slave connection, the FS and SCLK are input in which they need to be synchronized to each other

and programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to

synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data converter.

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