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IP1000A LF
Preliminary Data Sheet
2
Function Description
2.1
Physical Layer
2.1.1
Introduction
Figure 2-1 : DSP Function Block Diagram
10/100/1000
Transmit
PCS
TX_EN
TXD[7:0]
TX_ER
COL
TX_CLK
GTX_CLK
10/100/
1000
Receive
PCS
CRS
RX_CLK
RXD[7:0]
RX_ER
RX_DV
Balance
FIFO
NEXT
Canceller
Echo
Canceller
Hybrid
Baseline
Wander
Compensation
Gain
Control
ADC
De-skew
FIFO
FFE
DFE/VITERBI
Waveshape
Filter
DAC
DRIVER
Timing
Recovery
10BASE-T
Receiver
DPLL
Auto-Negotiation
Serial Interface
Management
PHY Registers
MDC
MDIO
INT#
TP_MDI[3:0]
With state-of-the-art DSP mixed-mode technology, the physical layer of IP1000A LF is designed to
accomplish low power, high performance, and full integration for 1000BASE-T, 100BASE-TX, and
10BASE-T operation.
The IP1000A LF eastablish a proper link mode with its link partner through Auto-Negotiation process.
Automatic MDI/MDI-X crossover function and wire polarity correction capability ensure robust data
exchange over CAT5 UTP cables. Channel skews among different pairs of the cable are also
automatically adjusted.
2.1.2
Receiver Fucntion
2.1.2.1
Active Hybrid
The IP1000A LF implements an on-chip hybrid to reduce the near-end echo by subtracting the replica of
the transmitted signal from the input signal. This hybrid relieves the precision requirement of ADC and
the digital echo canceller.
2.1.2.2
Analog to Digital Converter (ADC)
The ADC function block converts analog signal to digitized samples at 125MHz. With an advanced
architecture and high linearity, the ADC is able to provide excellent quantization accuracy for subsequent
digital signal processing.
10/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
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