IP1000A LF
Preliminary Data Sheet
62/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
2
DisableMemBase Disable Memory Base Address Register. DisableMemBase does not
correspond directly to any register accessible by the host system. If
DisableMemBase is a logic 1 during auto initialization of the IP1000A LF, the
MemBaseAddress register will be disabled. When disabled, the value
returned when the MemBaseAddress register is read is undefined.
3
D3ColdPme
D3 Cold Power Management Event. D3ColdPme corresponds to bit 15 of
the PmeSupport field within the PowerMgmtCap register.
4
D1Support
D1 Power State Support. D1Support corresponds to the D1Support bit of the
PowerMgmtCap register, and bit 12 of the PmeSupport field within the
PowerMgmtCap register.
5
D2Support
D2 Power State Support. D2Support corresponds to the D2Support bit of the
PowerMgmtCap register, and bit 13 of the PmeSupport field within the
PowerMgmtCap register.
6
PmeEn
Power Management Event Enable. PmeEn corresponds to the PmeEn bit in
the PowerMgmtCtrl register.
10..7
MinGnt
Minimum Grant. MinGnt corresponds to bits 7 through 4 of the MinGnt
register.
15..11 MaxLat
Maximum Latency. MaxLat corresponds to bits 5 through 1 of the Max-Lat
register.
3.2.3.2
AsicCtrl
Class............................. EEPROM Fields
I/O Base Address ......... 0x00, accessed via the EepromCtrl register
Address Offset .............. 0x01
Access Rule.................. Word
Width ............................ 16 bits
ASIC Control supplies the value for several bits of the AsicCtrl register and the WakeEvent register.
Bit
BIT Name
BIT Description
0
Exp-ROMDisable 0: Enable Exp-ROM. (Default)
1: Disable Exp-ROM.
1
Reserved
Reserved for future use.
2
Reserved
Reserved for future use. Write as zero, ignore on read.
3
Reserved
Reserved for future use. Write as zero, ignore on read.
4
PhySpeed10
Physical Layer Device Speed 10. PhySpeed10 corresponds to the
PhySpeed10 bit in the AsicCtrl register.
5
PhySpeed100
Physical Layer Device Speed 100. PhySpeed100 corresponds to the
PhySpeed100 bit in the AsicCtrl register.
6
PhySpeed1000
Physical Layer Device Speed 1000. PhySpeed1000 corresponds to the
PhySpeed1000 bit AsicCtrl register.
7
Reserved
Reserved for future use.
8
ForcedConfigMode 0: Enable EEPROM (Default)
1: Disable EEPROM
14..9
Reserved
Reserved for future use. Write as zero, ignore on read.
15
WakeOnLan-
Polarity
Wake-On-LAN
Polarity.
WakeOnLanPolarity
corresponds
to
the
WakeOnLanEnable bit in the WakeEvent register.
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