IP1000A LF
Preliminary Data Sheet
68/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
7
Switching Characteristics
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
66 MHz PCI Interface
Trc
RSTN cycle
300
ns
Trr
Rising Edge or RSTN to chip
recovery
1
µs
Tcc
PCICLK cycle
15
ns
Tch
PCICLK high
6
ns
Tcl
PCICLK low
6
ns
Trv
PCICLK rise to bused signal valid
2
6
ns
Trvp
PCICLK rise to REQN, GNTN valid
2
6
ns
Trzo
PCICLK rise to signal on
2
ns
Troz
PCICLK rise to signal off
14
ns
Tsu
bused signal setup wrt PCICLK rise
3
ns
Tsup1
GNTN setup wrt PCICLK rise
5
ns
Tsup2
REQN setup wrt PCICLK rise
5
ns
Thd
signal hold wrt PCICLK rise
0
ns
Trstoff
RSTN low to output signal float
40
ns
33MHz PCI Interface
Trc
RSTN cycle
300
ns
Trr
Rising edge or RSTN to chip
recovery
1
µs
Tcc
PCICLK cycle
30
ns
Tch
PCICLK high
11
ns
Tcl
PCICLK lwo
11
ns
Trv
PCICLK rise to bused signal valid
2
11
ns
Trvp
PCICLK rise to REQN, GNTN valid
2
12
ns
Trzo
PCICLK rise to signal on
2
ns
Troz
PCICLK rise to signal off
28
ns
Tsu
Bused signal setup wrt PCICLK rise
7
ns
Tsup1
GNTN setup wrt PCICLK rise
10
ns
Tsup2
REQN setup wrt PCICLK rise
12
ns
Thd
Signal hold wrt PCICLK rise
0
ns
Trstoff
RSTN low to output signal float
40
ns
Expansion Rom
fC
Clock Frequency for the following
instructions: FAST_READ, PP, SE,
BE, DP, RES, WREN, WRDI, RDSR,
WRSR
D.C.
25
MHz
fR
Clock Frequency for READ instructions
D.C.
20
MHz
tCH
1
Clock High Time
18
ns
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