IP1000A LF
Preliminary Data Sheet
53/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2.9
ExpRomBaseAddress
Class............................. PCI Configuration Registers, Configuration
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x30
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 0x32
ExpRomBaseAddress defines the base address for an Expansion ROM which may be interfaced to the
IP1000A LF.
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
0
AddressDecode-
Enable
Address
Decode
Enable.
When
AddressDecodeEnable is a logic 0 accesses to an
Expansion
ROM
are
disabled.
When
AddressDecodeEnable is a logic 1 and the
MemorySpace bit in the ConfigCommand register
is also a logic 1, accesses to an Expansion ROM
are enabled.
R/W
14..1
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
31..15 RomBaseAddress ROM Base Address. RomBaseAddress contains
the expansion ROM base address, or the upper
16 bits (or 15 bits, depending on the state of the
ExpRomSize bit in the AsicCtrl register) of the
Expansion
ROM
address
range.
If
the
ExpRomSize bit in the AsicCtrl register is a logic
0, all 16 bits of RomBaseAddress are valid. If the
ExpRomSize bit in the AsicCtrl register is a logic
1, bits 31 through 16 of RomBaseAddress are
valid, with bit 15 ignored (set to a logic 0) during
write operations.
R/W
3.2.2.10 HeaderType
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x0E
Default Value ................ 0x00
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
HeaderType
Header Type. HeaderType is set to 0x00 identifying
the IP1000A LF as a single-function PCI device
and specifying the configuration register layout.
R
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