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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
96/111
Mar 09, 2007
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14
MII0 MAC mode register
PHY
MII
ROM
R/W
Description
Default
31
3.15
--
RO
Flow control capability of the link partner of external PHY on MII0
1: link partner supports flow control,
0: link partner does not support flow control
1
31
3.14
--
RO
Mac_force[0]
1: MII0’s speed and duplex are forced because IP175C/IP175CH
finds external PHY doesn’t support SMI
0: MII0 polls external PHY through SMI to decide its speed and duplex.
31
3.13
--
RO
MII0_link
1: link ok, 0: un-link
31
3[12:8]
98[4:0]
R/W Capability of external PHY on MII0
bit12: flow control ability,
bit11: 100M full duplex,
bit10 : 100M half duplex,
bit9 : 10M full duplex,
bit8: 10M half duplex
11111
31
3.7
--
RO
Speed of external PHY on MII0
1: 10M,
0: 100M
0
31
3.6
--
RO
Duplex of external PHY on MII0
1: full duplex,
0: half duplex
0
31
3.5
--
RO
Link status of external PHY on MII0
1: link on,
0: link off
0
31
3[4:0]
97[4:0]
R/W MII0_mac_phy_addr
00000
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