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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
97/111
Mar 09, 2007
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14
MII1 MAC mode or MII2 MAC mode register (Only one is active at the same time.)
PHY
MII
ROM
R/W
Description
Default
31
4.15
--
RO
Flow control capability of the link partner of external PHY on MII1
MAC or MII2 MAC
1: link partner supports flow control,
0: link partner does not support flow control
1
31
4.14
--
RO
Mac_force[1]
1: MII1orMII2’s speed and duplex are forced because
IP175C/IP175CH finds external PHY doesn’t support SMI
0: MII1orMII2 polls external PHY through SMI to decide its
speed and duplex.
31
4.13
--
RO
MII1orMII2 _link
1: link ok, 0: un-link
31
4[12:8] 100[4:0] R/W Capability of external PHY on MII1 MAC or MII2 MAC
bit12: flow control ability,
bit11: 100M full duplex,
bit10 : 100M half duplex,
bit9 : 10M full duplex,
bit8: 10M half duplex
11111
31
4.7
--
RO
Speed of external PHY on MII1 MAC or MII2 MAC
1: 10M,
0: 100M
0
31
4.6
--
RO
Duplex of external PHY on MII1 MAC or MII2 MAC
1: full duplex,
0: half duplex
0
31
4.5
--
RO
Link status of external PHY on MII1 MAC or MII2 MAC
1: link on,
0: link off
0
31
4[4:0]
99[4:0]
R/W MII1orMII2_mac_phy_addr
00001
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