ADC12DL080CIVSSLASHNOPB datasheet(6/34 Pages) TI2

6 / 34 page

VDR

DR GND

AGND

DGND

AGND

ADC12DL080

SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

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Pin Descriptions and Equivalent Circuits (continued)

Pin No.

Symbol

Equivalent Circuit

Description

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

24–29

DA0–DA5

34–39

DA6-DA11

Digital data output pins that make up the 12-bit conversion results of

their respective converters. DA0 and DB0 are the LSBs, while DA11

and DB11 are the MSBs of the output word. Output levels are

42–47

DB0–DB5

TTL/CMOS compatible. Optimum loading is < 10pF.

52–57

DB6-DB11

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

9, 18, 19, 62,

quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors

located near the power pins, and with a 10 µF capacitor.

3, 8, 10, 17,

AGND

The ground return for the analog supply.

20, 61, 64

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

33, 48

quiet +3.3V source as is VA and be bypassed to DGND with a 0.1 µF

capacitor located near the power pins, and with a 10 µF capacitor.

32, 49

DGND

The ground return for the digital supply.

Positive driver supply pin for the ADC12DL080's output drivers. This

pin should be connected to a voltage source of +2.4V to VD and be

bypassed to DRGND with a 0.1 µF capacitor. This supply should

30, 51

VDR

also be bypassed with a 10 µF capacitor. VDR should never exceed

the voltage on VD. All 0.1 µF bypass capacitors should be located

near the supply pin.

The ground return for the digital supply for the ADC12DL080's output

drivers. These pins should be connected to the system digital

23, 31, 40,

DRGND

ground, but not be connected in close proximity to the

50, 58

ADC12DL080's DGND or AGND pins. See LAYOUT AND

GROUNDING (Layout and Grounding) for more details.

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