TLV2341IP datasheet(47/53 Pages) TI2

47 / 53 page

TLV2341, TLV2341Y

LinCMOS

™ PROGRAMMABLE LOW-VOLTAGE

OPERATIONAL AMPLIFIERS

SLOS110A – MAY 1992 – REVISED AUGUST 1994

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

bias selection

Bias selection is achieved by connecting the bias-select pin to one of the three voltage levels (see Figure 100).

For medium-bias applications, it is recommended that the bias-select pin be connected to the midpoint between

the supply rails. This is a simple procedure in split-supply applications, since this point is ground. In

single-supply applications, the medium-bias mode necessitates using a voltage divider as indicated. The use

of large-value resistors in the voltage divider reduces the current drain of the divider from the supply line.

However, large-value resistors used in conjunction with a large-value capacitor require significant time to charge

up to the supply midpoint after the supply is switched on. A voltage other than the midpoint may be used if it

is within the voltages specified in the following table.

BIAS MODE

BIAS-SELECT VOLTAGE

(single supply)

Low

VDD

Medium

1 V to VDD –1 V

High

GND

Figure 100. Bias Selection for Single-Supply Applications

input characteristics

The TLV2341 is specified with a minimum and a maximum input voltage that, if exceeded at either input, could

cause the device to malfunction. Exceeding this specified range is a common problem, especially in

single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is

specified at VDD –1 V at TA = 25°C and at VDD –1.2 V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TLV2341 good input offset

voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices

is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in

the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization

problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with

time has been calculated to be typically 0.1

µV/month, including the first month of operation.

Because of the extremely high input impedance and resulting low bias-current requirements, the TLV2341 is

well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can

easily exceed bias-current requirements and cause a degradation in device performance. It is good practice

to include guard rings around inputs (similar to those of Figure 95 in the Parameter Measurement Information

section). These guards should be driven from a low-impedance source at the same voltage level as the

common-mode input (see Figure 101).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

To BIAS SELECT

Low

High

Medium

1 M

Ω

VDD

1 M

Ω

0.01

µF

TLV2341IP 数据表(PDF) 47 Page - Texas Instruments

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