| 数据搜索系统,热门电子元器件搜索 |
|
BQ27Z561-R2 数据表(PDF) 5 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
BQ27Z561-R2 数据表(HTML) 5 Page - Texas Instruments |
|
5 / 27 page ![]() 7.4 Thermal Information Over-operating free-air temperature range (unless otherwise noted) THERMAL METRIC(1) BQ27Z561-R2 UNIT DSBGA (YPH) (12 PINS) RθJA Junction-to-ambient thermal resistance 64.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 59.8 RθJB Junction-to-board thermal resistance 52.7 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 28.3 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application Report. 7.5 Supply Current Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INORMAL Standard operating conditions 60 µA ISLEEP Sense resistor current below SLEEP mode threshold 11 µA IDEEPSLEEP Sense resistor current below DEEP SLEEP mode threshold 9 µA IHIBERNATE CE = VIH, OFF state with ability to wake from valid communication 3 µA IOFF CE = VIL 0.5 µA 7.6 Internal 1.8-V LDO (REG18) Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREG18 Regulator output voltage 1.6 1.8 2.0 V VPORth POR threshold Rising threshold 1.45 1.7 V VPORhy POR hysteresis 0.1 V 7.7 I/O (PULS, INT) Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage VREG18 = 1.8 V 1.15 V VIL Low-level input voltage low VREG18 = 1.8 V 0.50 V VOL Output voltage low VREG18 = 1.8 V, IOL = 1 mA 0.4 V CI Input capacitance 5 pF Ilkg Input leakage current 1 µA 7.8 Chip Enable (CE) Unless otherwise noted, characteristics noted under conditions of TA = –40℃ to 85℃ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage (assured by design) VREG18 = 1.8 V 0.75 × VBAT V VIL Low-level input voltage low (assured by design) VREG18 = 1.8 V 0.25 × VBAT V www.ti.com BQ27Z561-R2 SLUSE22B – FEBRUARY 2020 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: BQ27Z561-R2 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |