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ST10F271Z1 数据表(PDF) 59 Page - STMicroelectronics |
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ST10F271Z1 数据表(HTML) 59 Page - STMicroelectronics |
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59 / 185 page ![]() ST10F271Z1 General purpose timer unit 59/185 Figure 10. Block diagram of GPT1 11.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflow / underflow of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. Table 35. GPT1 timer input frequencies, resolutions and periods at 64 MHz fCPU = 64 MHz Timer input selection T2I / T3I / T4I 000b 001b 010b 011b 100b 101b 110b 111b Prescaler factor 8 16 32 64 128 256 512 1024 Input freq 8 MHz 4 MHz 2 MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125 ns 250 ns 0.5 µs 1.0 µs 2.0 µs 4.0 µs 8.0 µs 16.0 µs Period maximum 8.2 ms 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1.049 s 2n n=3...10 2n n=3...10 2n n=3...10 T2EUD T2IN CPU clock CPU clock CPU clock T3IN T4IN T3EUD T4EUD GPT1 Timer T2 GPT1 Timer T3 GPT1 Timer T4 T3OTL Reload Capture U/D U/D Reload Capture Interrupt Request Interrupt Request Interrupt Request T3OUT U/D T2 Mode Control T3 Mode Control T4 Mode Control |
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