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ST10F271Z1 数据表(PDF) 19 Page - STMicroelectronics |
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ST10F271Z1 数据表(HTML) 19 Page - STMicroelectronics |
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19 / 185 page ![]() ST10F271Z1 Functional description 19/185 3 Functional description The architecture of the ST10F271Z1 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F271Z1. Figure 3. Block diagram 4-8 MHz BRG BRG Port 6 Port 5 CPU-Core and MAC Unit XCAN2 XSSC XASC XCAN1 XI2C XRAM 2K XRAM 8K (STBY) (PEC) IFlash 128K 32 16 16 16 16 16 16 16 16 PEC Interrupt Controller Port 3 Port 7 Port 8 16 Watchdog IRAM 2K 16 XRTC PLL 5V-1.8V Voltage Regulator 16 16 8 816 15 8 8 16 16 32kHz Oscillator XPWM 16 16 Oscillator |
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